2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
45 #include <asm/proto.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
53 #include <mach_apic.h>
58 unsigned move_cleanup_count;
60 u8 move_in_progress : 1;
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
83 static int assign_irq_vector(int irq, cpumask_t mask);
85 #define __apicdebuginit __init
87 int sis_apic_bug; /* not actually supported, dummy for compile */
89 static int no_timer_check;
91 static int disable_timer_pin_1 __initdata;
93 int timer_through_8259 __initdata;
95 /* Where if anywhere is the i8259 connect in external int mode */
96 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
98 static DEFINE_SPINLOCK(ioapic_lock);
99 DEFINE_SPINLOCK(vector_lock);
102 * # of IRQ routing registers
104 int nr_ioapic_registers[MAX_IO_APICS];
106 /* I/O APIC entries */
107 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
110 /* MP IRQ source entries */
111 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
113 /* # of MP IRQ source entries */
117 * Rough estimation of how many shared IRQs there are, can
118 * be changed anytime.
120 #define MAX_PLUS_SHARED_IRQS NR_IRQS
121 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
124 * This is performance-critical, we want to do it O(1)
126 * the indexing order of this array favors 1:1 mappings
127 * between pins and IRQs.
130 static struct irq_pin_list {
131 short apic, pin, next;
132 } irq_2_pin[PIN_MAP_SIZE];
136 unsigned int unused[3];
140 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
142 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
143 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
146 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
148 struct io_apic __iomem *io_apic = io_apic_base(apic);
149 writel(reg, &io_apic->index);
150 return readl(&io_apic->data);
153 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
155 struct io_apic __iomem *io_apic = io_apic_base(apic);
156 writel(reg, &io_apic->index);
157 writel(value, &io_apic->data);
161 * Re-write a value: to be used for read-modify-write
162 * cycles where the read already set up the index register.
164 static inline void io_apic_modify(unsigned int apic, unsigned int value)
166 struct io_apic __iomem *io_apic = io_apic_base(apic);
167 writel(value, &io_apic->data);
170 static bool io_apic_level_ack_pending(unsigned int irq)
172 struct irq_pin_list *entry;
175 spin_lock_irqsave(&ioapic_lock, flags);
176 entry = irq_2_pin + irq;
184 reg = io_apic_read(entry->apic, 0x10 + pin*2);
185 /* Is the remote IRR bit set? */
186 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
187 spin_unlock_irqrestore(&ioapic_lock, flags);
192 entry = irq_2_pin + entry->next;
194 spin_unlock_irqrestore(&ioapic_lock, flags);
200 * Synchronize the IO-APIC and the CPU by doing
201 * a dummy read from the IO-APIC
203 static inline void io_apic_sync(unsigned int apic)
205 struct io_apic __iomem *io_apic = io_apic_base(apic);
206 readl(&io_apic->data);
209 #define __DO_ACTION(R, ACTION, FINAL) \
213 struct irq_pin_list *entry = irq_2_pin + irq; \
215 BUG_ON(irq >= NR_IRQS); \
221 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
223 io_apic_modify(entry->apic, reg); \
227 entry = irq_2_pin + entry->next; \
232 struct { u32 w1, w2; };
233 struct IO_APIC_route_entry entry;
236 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
238 union entry_union eu;
240 spin_lock_irqsave(&ioapic_lock, flags);
241 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
242 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
248 * When we write a new IO APIC routing entry, we need to write the high
249 * word first! If the mask bit in the low word is clear, we will enable
250 * the interrupt, and we need to make sure the entry is fully populated
251 * before that happens.
254 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
256 union entry_union eu;
258 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
259 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
262 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
265 spin_lock_irqsave(&ioapic_lock, flags);
266 __ioapic_write_entry(apic, pin, e);
267 spin_unlock_irqrestore(&ioapic_lock, flags);
271 * When we mask an IO APIC routing entry, we need to write the low
272 * word first, in order to set the mask bit before we change the
275 static void ioapic_mask_entry(int apic, int pin)
278 union entry_union eu = { .entry.mask = 1 };
280 spin_lock_irqsave(&ioapic_lock, flags);
281 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
282 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
283 spin_unlock_irqrestore(&ioapic_lock, flags);
287 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
290 struct irq_pin_list *entry = irq_2_pin + irq;
292 BUG_ON(irq >= NR_IRQS);
299 io_apic_write(apic, 0x11 + pin*2, dest);
300 reg = io_apic_read(apic, 0x10 + pin*2);
301 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
303 io_apic_modify(apic, reg);
306 entry = irq_2_pin + entry->next;
310 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
312 struct irq_cfg *cfg = irq_cfg + irq;
317 cpus_and(tmp, mask, cpu_online_map);
321 if (assign_irq_vector(irq, mask))
324 cpus_and(tmp, cfg->domain, mask);
325 dest = cpu_mask_to_apicid(tmp);
328 * Only the high 8 bits are valid.
330 dest = SET_APIC_LOGICAL_ID(dest);
332 spin_lock_irqsave(&ioapic_lock, flags);
333 __target_IO_APIC_irq(irq, dest, cfg->vector);
334 irq_desc[irq].affinity = mask;
335 spin_unlock_irqrestore(&ioapic_lock, flags);
340 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
341 * shared ISA-space IRQs, so we have to support them. We are super
342 * fast in the common case, and fast for shared ISA-space IRQs.
344 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
346 static int first_free_entry = NR_IRQS;
347 struct irq_pin_list *entry = irq_2_pin + irq;
349 BUG_ON(irq >= NR_IRQS);
351 entry = irq_2_pin + entry->next;
353 if (entry->pin != -1) {
354 entry->next = first_free_entry;
355 entry = irq_2_pin + entry->next;
356 if (++first_free_entry >= PIN_MAP_SIZE)
357 panic("io_apic.c: ran out of irq_2_pin entries!");
364 * Reroute an IRQ to a different pin.
366 static void __init replace_pin_at_irq(unsigned int irq,
367 int oldapic, int oldpin,
368 int newapic, int newpin)
370 struct irq_pin_list *entry = irq_2_pin + irq;
373 if (entry->apic == oldapic && entry->pin == oldpin) {
374 entry->apic = newapic;
379 entry = irq_2_pin + entry->next;
384 #define DO_ACTION(name,R,ACTION, FINAL) \
386 static void name##_IO_APIC_irq (unsigned int irq) \
387 __DO_ACTION(R, ACTION, FINAL)
390 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
393 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
395 static void mask_IO_APIC_irq (unsigned int irq)
399 spin_lock_irqsave(&ioapic_lock, flags);
400 __mask_IO_APIC_irq(irq);
401 spin_unlock_irqrestore(&ioapic_lock, flags);
404 static void unmask_IO_APIC_irq (unsigned int irq)
408 spin_lock_irqsave(&ioapic_lock, flags);
409 __unmask_IO_APIC_irq(irq);
410 spin_unlock_irqrestore(&ioapic_lock, flags);
413 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
415 struct IO_APIC_route_entry entry;
417 /* Check delivery_mode to be sure we're not clearing an SMI pin */
418 entry = ioapic_read_entry(apic, pin);
419 if (entry.delivery_mode == dest_SMI)
422 * Disable it in the IO-APIC irq-routing table:
424 ioapic_mask_entry(apic, pin);
427 static void clear_IO_APIC (void)
431 for (apic = 0; apic < nr_ioapics; apic++)
432 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
433 clear_IO_APIC_pin(apic, pin);
436 int skip_ioapic_setup;
439 static int __init parse_noapic(char *str)
441 disable_ioapic_setup();
444 early_param("noapic", parse_noapic);
446 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
447 static int __init disable_timer_pin_setup(char *arg)
449 disable_timer_pin_1 = 1;
452 __setup("disable_timer_pin_1", disable_timer_pin_setup);
456 * Find the IRQ entry number of a certain pin.
458 static int find_irq_entry(int apic, int pin, int type)
462 for (i = 0; i < mp_irq_entries; i++)
463 if (mp_irqs[i].mpc_irqtype == type &&
464 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
465 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
466 mp_irqs[i].mpc_dstirq == pin)
473 * Find the pin to which IRQ[irq] (ISA) is connected
475 static int __init find_isa_irq_pin(int irq, int type)
479 for (i = 0; i < mp_irq_entries; i++) {
480 int lbus = mp_irqs[i].mpc_srcbus;
482 if (test_bit(lbus, mp_bus_not_pci) &&
483 (mp_irqs[i].mpc_irqtype == type) &&
484 (mp_irqs[i].mpc_srcbusirq == irq))
486 return mp_irqs[i].mpc_dstirq;
491 static int __init find_isa_irq_apic(int irq, int type)
495 for (i = 0; i < mp_irq_entries; i++) {
496 int lbus = mp_irqs[i].mpc_srcbus;
498 if (test_bit(lbus, mp_bus_not_pci) &&
499 (mp_irqs[i].mpc_irqtype == type) &&
500 (mp_irqs[i].mpc_srcbusirq == irq))
503 if (i < mp_irq_entries) {
505 for(apic = 0; apic < nr_ioapics; apic++) {
506 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
515 * Find a specific PCI IRQ entry.
516 * Not an __init, possibly needed by modules
518 static int pin_2_irq(int idx, int apic, int pin);
520 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
522 int apic, i, best_guess = -1;
524 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
526 if (mp_bus_id_to_pci_bus[bus] == -1) {
527 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
530 for (i = 0; i < mp_irq_entries; i++) {
531 int lbus = mp_irqs[i].mpc_srcbus;
533 for (apic = 0; apic < nr_ioapics; apic++)
534 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
535 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
538 if (!test_bit(lbus, mp_bus_not_pci) &&
539 !mp_irqs[i].mpc_irqtype &&
541 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
542 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
544 if (!(apic || IO_APIC_IRQ(irq)))
547 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
550 * Use the first all-but-pin matching entry as a
551 * best-guess fuzzy result for broken mptables.
557 BUG_ON(best_guess >= NR_IRQS);
561 /* ISA interrupts are always polarity zero edge triggered,
562 * when listed as conforming in the MP table. */
564 #define default_ISA_trigger(idx) (0)
565 #define default_ISA_polarity(idx) (0)
567 /* PCI interrupts are always polarity one level triggered,
568 * when listed as conforming in the MP table. */
570 #define default_PCI_trigger(idx) (1)
571 #define default_PCI_polarity(idx) (1)
573 static int MPBIOS_polarity(int idx)
575 int bus = mp_irqs[idx].mpc_srcbus;
579 * Determine IRQ line polarity (high active or low active):
581 switch (mp_irqs[idx].mpc_irqflag & 3)
583 case 0: /* conforms, ie. bus-type dependent polarity */
584 if (test_bit(bus, mp_bus_not_pci))
585 polarity = default_ISA_polarity(idx);
587 polarity = default_PCI_polarity(idx);
589 case 1: /* high active */
594 case 2: /* reserved */
596 printk(KERN_WARNING "broken BIOS!!\n");
600 case 3: /* low active */
605 default: /* invalid */
607 printk(KERN_WARNING "broken BIOS!!\n");
615 static int MPBIOS_trigger(int idx)
617 int bus = mp_irqs[idx].mpc_srcbus;
621 * Determine IRQ trigger mode (edge or level sensitive):
623 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
625 case 0: /* conforms, ie. bus-type dependent */
626 if (test_bit(bus, mp_bus_not_pci))
627 trigger = default_ISA_trigger(idx);
629 trigger = default_PCI_trigger(idx);
636 case 2: /* reserved */
638 printk(KERN_WARNING "broken BIOS!!\n");
647 default: /* invalid */
649 printk(KERN_WARNING "broken BIOS!!\n");
657 static inline int irq_polarity(int idx)
659 return MPBIOS_polarity(idx);
662 static inline int irq_trigger(int idx)
664 return MPBIOS_trigger(idx);
667 static int pin_2_irq(int idx, int apic, int pin)
670 int bus = mp_irqs[idx].mpc_srcbus;
673 * Debugging check, we are in big trouble if this message pops up!
675 if (mp_irqs[idx].mpc_dstirq != pin)
676 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
678 if (test_bit(bus, mp_bus_not_pci)) {
679 irq = mp_irqs[idx].mpc_srcbusirq;
682 * PCI IRQs are mapped in order
686 irq += nr_ioapic_registers[i++];
689 BUG_ON(irq >= NR_IRQS);
693 static int __assign_irq_vector(int irq, cpumask_t mask)
696 * NOTE! The local APIC isn't very good at handling
697 * multiple interrupts at the same interrupt level.
698 * As the interrupt level is determined by taking the
699 * vector number and shifting that right by 4, we
700 * want to spread these out a bit so that they don't
701 * all fall in the same interrupt level.
703 * Also, we've got to be careful not to trash gate
704 * 0x80, because int 0x80 is hm, kind of importantish. ;)
706 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
707 unsigned int old_vector;
711 BUG_ON((unsigned)irq >= NR_IRQS);
714 /* Only try and allocate irqs on cpus that are present */
715 cpus_and(mask, mask, cpu_online_map);
717 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
720 old_vector = cfg->vector;
723 cpus_and(tmp, cfg->domain, mask);
724 if (!cpus_empty(tmp))
728 for_each_cpu_mask(cpu, mask) {
729 cpumask_t domain, new_mask;
733 domain = vector_allocation_domain(cpu);
734 cpus_and(new_mask, domain, cpu_online_map);
736 vector = current_vector;
737 offset = current_offset;
740 if (vector >= FIRST_SYSTEM_VECTOR) {
741 /* If we run out of vectors on large boxen, must share them. */
742 offset = (offset + 1) % 8;
743 vector = FIRST_DEVICE_VECTOR + offset;
745 if (unlikely(current_vector == vector))
747 if (vector == IA32_SYSCALL_VECTOR)
749 for_each_cpu_mask(new_cpu, new_mask)
750 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
753 current_vector = vector;
754 current_offset = offset;
756 cfg->move_in_progress = 1;
757 cfg->old_domain = cfg->domain;
759 for_each_cpu_mask(new_cpu, new_mask)
760 per_cpu(vector_irq, new_cpu)[vector] = irq;
761 cfg->vector = vector;
762 cfg->domain = domain;
768 static int assign_irq_vector(int irq, cpumask_t mask)
773 spin_lock_irqsave(&vector_lock, flags);
774 err = __assign_irq_vector(irq, mask);
775 spin_unlock_irqrestore(&vector_lock, flags);
779 static void __clear_irq_vector(int irq)
785 BUG_ON((unsigned)irq >= NR_IRQS);
787 BUG_ON(!cfg->vector);
789 vector = cfg->vector;
790 cpus_and(mask, cfg->domain, cpu_online_map);
791 for_each_cpu_mask(cpu, mask)
792 per_cpu(vector_irq, cpu)[vector] = -1;
795 cpus_clear(cfg->domain);
798 void __setup_vector_irq(int cpu)
800 /* Initialize vector_irq on a new cpu */
801 /* This function must be called with vector_lock held */
804 /* Mark the inuse vectors */
805 for (irq = 0; irq < NR_IRQS; ++irq) {
806 if (!cpu_isset(cpu, irq_cfg[irq].domain))
808 vector = irq_cfg[irq].vector;
809 per_cpu(vector_irq, cpu)[vector] = irq;
811 /* Mark the free vectors */
812 for (vector = 0; vector < NR_VECTORS; ++vector) {
813 irq = per_cpu(vector_irq, cpu)[vector];
816 if (!cpu_isset(cpu, irq_cfg[irq].domain))
817 per_cpu(vector_irq, cpu)[vector] = -1;
822 static struct irq_chip ioapic_chip;
824 static void ioapic_register_intr(int irq, unsigned long trigger)
827 irq_desc[irq].status |= IRQ_LEVEL;
828 set_irq_chip_and_handler_name(irq, &ioapic_chip,
829 handle_fasteoi_irq, "fasteoi");
831 irq_desc[irq].status &= ~IRQ_LEVEL;
832 set_irq_chip_and_handler_name(irq, &ioapic_chip,
833 handle_edge_irq, "edge");
837 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
838 int trigger, int polarity)
840 struct irq_cfg *cfg = irq_cfg + irq;
841 struct IO_APIC_route_entry entry;
844 if (!IO_APIC_IRQ(irq))
848 if (assign_irq_vector(irq, mask))
851 cpus_and(mask, cfg->domain, mask);
853 apic_printk(APIC_VERBOSE,KERN_DEBUG
854 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
855 "IRQ %d Mode:%i Active:%i)\n",
856 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
857 irq, trigger, polarity);
860 * add it to the IO-APIC irq-routing table:
862 memset(&entry,0,sizeof(entry));
864 entry.delivery_mode = INT_DELIVERY_MODE;
865 entry.dest_mode = INT_DEST_MODE;
866 entry.dest = cpu_mask_to_apicid(mask);
867 entry.mask = 0; /* enable IRQ */
868 entry.trigger = trigger;
869 entry.polarity = polarity;
870 entry.vector = cfg->vector;
872 /* Mask level triggered irqs.
873 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
878 ioapic_register_intr(irq, trigger);
880 disable_8259A_irq(irq);
882 ioapic_write_entry(apic, pin, entry);
885 static void __init setup_IO_APIC_irqs(void)
887 int apic, pin, idx, irq, first_notcon = 1;
889 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
891 for (apic = 0; apic < nr_ioapics; apic++) {
892 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
894 idx = find_irq_entry(apic,pin,mp_INT);
897 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
900 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
904 apic_printk(APIC_VERBOSE, " not connected.\n");
908 irq = pin_2_irq(idx, apic, pin);
909 add_pin_to_irq(irq, apic, pin);
911 setup_IO_APIC_irq(apic, pin, irq,
912 irq_trigger(idx), irq_polarity(idx));
917 apic_printk(APIC_VERBOSE, " not connected.\n");
921 * Set up the timer pin, possibly with the 8259A-master behind.
923 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
926 struct IO_APIC_route_entry entry;
928 memset(&entry, 0, sizeof(entry));
931 * We use logical delivery to get the timer IRQ
934 entry.dest_mode = INT_DEST_MODE;
935 entry.mask = 1; /* mask IRQ now */
936 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
937 entry.delivery_mode = INT_DELIVERY_MODE;
940 entry.vector = vector;
943 * The timer IRQ doesn't have to know that behind the
944 * scene we may have a 8259A-master in AEOI mode ...
946 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
949 * Add it to the IO-APIC irq-routing table:
951 ioapic_write_entry(apic, pin, entry);
954 void __apicdebuginit print_IO_APIC(void)
957 union IO_APIC_reg_00 reg_00;
958 union IO_APIC_reg_01 reg_01;
959 union IO_APIC_reg_02 reg_02;
962 if (apic_verbosity == APIC_QUIET)
965 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
966 for (i = 0; i < nr_ioapics; i++)
967 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
968 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
971 * We are a bit conservative about what we expect. We have to
972 * know about every hardware change ASAP.
974 printk(KERN_INFO "testing the IO APIC.......................\n");
976 for (apic = 0; apic < nr_ioapics; apic++) {
978 spin_lock_irqsave(&ioapic_lock, flags);
979 reg_00.raw = io_apic_read(apic, 0);
980 reg_01.raw = io_apic_read(apic, 1);
981 if (reg_01.bits.version >= 0x10)
982 reg_02.raw = io_apic_read(apic, 2);
983 spin_unlock_irqrestore(&ioapic_lock, flags);
986 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
987 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
988 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
990 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
991 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
993 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
994 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
996 if (reg_01.bits.version >= 0x10) {
997 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
998 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1001 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1003 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1004 " Stat Dmod Deli Vect: \n");
1006 for (i = 0; i <= reg_01.bits.entries; i++) {
1007 struct IO_APIC_route_entry entry;
1009 entry = ioapic_read_entry(apic, i);
1011 printk(KERN_DEBUG " %02x %03X ",
1016 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1021 entry.delivery_status,
1023 entry.delivery_mode,
1028 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1029 for (i = 0; i < NR_IRQS; i++) {
1030 struct irq_pin_list *entry = irq_2_pin + i;
1033 printk(KERN_DEBUG "IRQ%d ", i);
1035 printk("-> %d:%d", entry->apic, entry->pin);
1038 entry = irq_2_pin + entry->next;
1043 printk(KERN_INFO ".................................... done.\n");
1050 static __apicdebuginit void print_APIC_bitfield (int base)
1055 if (apic_verbosity == APIC_QUIET)
1058 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1059 for (i = 0; i < 8; i++) {
1060 v = apic_read(base + i*0x10);
1061 for (j = 0; j < 32; j++) {
1071 void __apicdebuginit print_local_APIC(void * dummy)
1073 unsigned int v, ver, maxlvt;
1075 if (apic_verbosity == APIC_QUIET)
1078 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1079 smp_processor_id(), hard_smp_processor_id());
1080 v = apic_read(APIC_ID);
1081 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1082 v = apic_read(APIC_LVR);
1083 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1084 ver = GET_APIC_VERSION(v);
1085 maxlvt = lapic_get_maxlvt();
1087 v = apic_read(APIC_TASKPRI);
1088 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1090 v = apic_read(APIC_ARBPRI);
1091 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1092 v & APIC_ARBPRI_MASK);
1093 v = apic_read(APIC_PROCPRI);
1094 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1096 v = apic_read(APIC_EOI);
1097 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1098 v = apic_read(APIC_RRR);
1099 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1100 v = apic_read(APIC_LDR);
1101 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1102 v = apic_read(APIC_DFR);
1103 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1104 v = apic_read(APIC_SPIV);
1105 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1107 printk(KERN_DEBUG "... APIC ISR field:\n");
1108 print_APIC_bitfield(APIC_ISR);
1109 printk(KERN_DEBUG "... APIC TMR field:\n");
1110 print_APIC_bitfield(APIC_TMR);
1111 printk(KERN_DEBUG "... APIC IRR field:\n");
1112 print_APIC_bitfield(APIC_IRR);
1114 v = apic_read(APIC_ESR);
1115 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1117 v = apic_read(APIC_ICR);
1118 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1119 v = apic_read(APIC_ICR2);
1120 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1122 v = apic_read(APIC_LVTT);
1123 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1125 if (maxlvt > 3) { /* PC is LVT#4. */
1126 v = apic_read(APIC_LVTPC);
1127 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1129 v = apic_read(APIC_LVT0);
1130 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1131 v = apic_read(APIC_LVT1);
1132 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1134 if (maxlvt > 2) { /* ERR is LVT#3. */
1135 v = apic_read(APIC_LVTERR);
1136 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1139 v = apic_read(APIC_TMICT);
1140 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1141 v = apic_read(APIC_TMCCT);
1142 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1143 v = apic_read(APIC_TDCR);
1144 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1148 void print_all_local_APICs (void)
1150 on_each_cpu(print_local_APIC, NULL, 1, 1);
1153 void __apicdebuginit print_PIC(void)
1156 unsigned long flags;
1158 if (apic_verbosity == APIC_QUIET)
1161 printk(KERN_DEBUG "\nprinting PIC contents\n");
1163 spin_lock_irqsave(&i8259A_lock, flags);
1165 v = inb(0xa1) << 8 | inb(0x21);
1166 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1168 v = inb(0xa0) << 8 | inb(0x20);
1169 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1173 v = inb(0xa0) << 8 | inb(0x20);
1177 spin_unlock_irqrestore(&i8259A_lock, flags);
1179 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1181 v = inb(0x4d1) << 8 | inb(0x4d0);
1182 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1187 void __init enable_IO_APIC(void)
1189 union IO_APIC_reg_01 reg_01;
1190 int i8259_apic, i8259_pin;
1192 unsigned long flags;
1194 for (i = 0; i < PIN_MAP_SIZE; i++) {
1195 irq_2_pin[i].pin = -1;
1196 irq_2_pin[i].next = 0;
1200 * The number of IO-APIC IRQ registers (== #pins):
1202 for (apic = 0; apic < nr_ioapics; apic++) {
1203 spin_lock_irqsave(&ioapic_lock, flags);
1204 reg_01.raw = io_apic_read(apic, 1);
1205 spin_unlock_irqrestore(&ioapic_lock, flags);
1206 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1208 for(apic = 0; apic < nr_ioapics; apic++) {
1210 /* See if any of the pins is in ExtINT mode */
1211 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1212 struct IO_APIC_route_entry entry;
1213 entry = ioapic_read_entry(apic, pin);
1215 /* If the interrupt line is enabled and in ExtInt mode
1216 * I have found the pin where the i8259 is connected.
1218 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1219 ioapic_i8259.apic = apic;
1220 ioapic_i8259.pin = pin;
1226 /* Look to see what if the MP table has reported the ExtINT */
1227 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1228 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1229 /* Trust the MP table if nothing is setup in the hardware */
1230 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1231 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1232 ioapic_i8259.pin = i8259_pin;
1233 ioapic_i8259.apic = i8259_apic;
1235 /* Complain if the MP table and the hardware disagree */
1236 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1237 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1239 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1243 * Do not trust the IO-APIC being empty at bootup
1249 * Not an __init, needed by the reboot code
1251 void disable_IO_APIC(void)
1254 * Clear the IO-APIC before rebooting:
1259 * If the i8259 is routed through an IOAPIC
1260 * Put that IOAPIC in virtual wire mode
1261 * so legacy interrupts can be delivered.
1263 if (ioapic_i8259.pin != -1) {
1264 struct IO_APIC_route_entry entry;
1266 memset(&entry, 0, sizeof(entry));
1267 entry.mask = 0; /* Enabled */
1268 entry.trigger = 0; /* Edge */
1270 entry.polarity = 0; /* High */
1271 entry.delivery_status = 0;
1272 entry.dest_mode = 0; /* Physical */
1273 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1275 entry.dest = GET_APIC_ID(read_apic_id());
1278 * Add it to the IO-APIC irq-routing table:
1280 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1283 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1287 * There is a nasty bug in some older SMP boards, their mptable lies
1288 * about the timer IRQ. We do the following to work around the situation:
1290 * - timer IRQ defaults to IO-APIC IRQ
1291 * - if this function detects that timer IRQs are defunct, then we fall
1292 * back to ISA timer IRQs
1294 static int __init timer_irq_works(void)
1296 unsigned long t1 = jiffies;
1297 unsigned long flags;
1299 local_save_flags(flags);
1301 /* Let ten ticks pass... */
1302 mdelay((10 * 1000) / HZ);
1303 local_irq_restore(flags);
1306 * Expect a few ticks at least, to be sure some possible
1307 * glue logic does not lock up after one or two first
1308 * ticks in a non-ExtINT mode. Also the local APIC
1309 * might have cached one ExtINT interrupt. Finally, at
1310 * least one tick may be lost due to delays.
1314 if (time_after(jiffies, t1 + 4))
1320 * In the SMP+IOAPIC case it might happen that there are an unspecified
1321 * number of pending IRQ events unhandled. These cases are very rare,
1322 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1323 * better to do it this way as thus we do not have to be aware of
1324 * 'pending' interrupts in the IRQ path, except at this point.
1327 * Edge triggered needs to resend any interrupt
1328 * that was delayed but this is now handled in the device
1333 * Starting up a edge-triggered IO-APIC interrupt is
1334 * nasty - we need to make sure that we get the edge.
1335 * If it is already asserted for some reason, we need
1336 * return 1 to indicate that is was pending.
1338 * This is not complete - we should be able to fake
1339 * an edge even if it isn't on the 8259A...
1342 static unsigned int startup_ioapic_irq(unsigned int irq)
1344 int was_pending = 0;
1345 unsigned long flags;
1347 spin_lock_irqsave(&ioapic_lock, flags);
1349 disable_8259A_irq(irq);
1350 if (i8259A_irq_pending(irq))
1353 __unmask_IO_APIC_irq(irq);
1354 spin_unlock_irqrestore(&ioapic_lock, flags);
1359 static int ioapic_retrigger_irq(unsigned int irq)
1361 struct irq_cfg *cfg = &irq_cfg[irq];
1363 unsigned long flags;
1365 spin_lock_irqsave(&vector_lock, flags);
1366 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1367 send_IPI_mask(mask, cfg->vector);
1368 spin_unlock_irqrestore(&vector_lock, flags);
1374 * Level and edge triggered IO-APIC interrupts need different handling,
1375 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1376 * handled with the level-triggered descriptor, but that one has slightly
1377 * more overhead. Level-triggered interrupts cannot be handled with the
1378 * edge-triggered handler, without risking IRQ storms and other ugly
1383 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1385 unsigned vector, me;
1390 me = smp_processor_id();
1391 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1393 struct irq_desc *desc;
1394 struct irq_cfg *cfg;
1395 irq = __get_cpu_var(vector_irq)[vector];
1399 desc = irq_desc + irq;
1400 cfg = irq_cfg + irq;
1401 spin_lock(&desc->lock);
1402 if (!cfg->move_cleanup_count)
1405 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1408 __get_cpu_var(vector_irq)[vector] = -1;
1409 cfg->move_cleanup_count--;
1411 spin_unlock(&desc->lock);
1417 static void irq_complete_move(unsigned int irq)
1419 struct irq_cfg *cfg = irq_cfg + irq;
1420 unsigned vector, me;
1422 if (likely(!cfg->move_in_progress))
1425 vector = ~get_irq_regs()->orig_ax;
1426 me = smp_processor_id();
1427 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1428 cpumask_t cleanup_mask;
1430 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1431 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1432 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1433 cfg->move_in_progress = 0;
1437 static inline void irq_complete_move(unsigned int irq) {}
1440 static void ack_apic_edge(unsigned int irq)
1442 irq_complete_move(irq);
1443 move_native_irq(irq);
1447 static void ack_apic_level(unsigned int irq)
1449 int do_unmask_irq = 0;
1451 irq_complete_move(irq);
1452 #ifdef CONFIG_GENERIC_PENDING_IRQ
1453 /* If we are moving the irq we need to mask it */
1454 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1456 mask_IO_APIC_irq(irq);
1461 * We must acknowledge the irq before we move it or the acknowledge will
1462 * not propagate properly.
1466 /* Now we can move and renable the irq */
1467 if (unlikely(do_unmask_irq)) {
1468 /* Only migrate the irq if the ack has been received.
1470 * On rare occasions the broadcast level triggered ack gets
1471 * delayed going to ioapics, and if we reprogram the
1472 * vector while Remote IRR is still set the irq will never
1475 * To prevent this scenario we read the Remote IRR bit
1476 * of the ioapic. This has two effects.
1477 * - On any sane system the read of the ioapic will
1478 * flush writes (and acks) going to the ioapic from
1480 * - We get to see if the ACK has actually been delivered.
1482 * Based on failed experiments of reprogramming the
1483 * ioapic entry from outside of irq context starting
1484 * with masking the ioapic entry and then polling until
1485 * Remote IRR was clear before reprogramming the
1486 * ioapic I don't trust the Remote IRR bit to be
1487 * completey accurate.
1489 * However there appears to be no other way to plug
1490 * this race, so if the Remote IRR bit is not
1491 * accurate and is causing problems then it is a hardware bug
1492 * and you can go talk to the chipset vendor about it.
1494 if (!io_apic_level_ack_pending(irq))
1495 move_masked_irq(irq);
1496 unmask_IO_APIC_irq(irq);
1500 static struct irq_chip ioapic_chip __read_mostly = {
1502 .startup = startup_ioapic_irq,
1503 .mask = mask_IO_APIC_irq,
1504 .unmask = unmask_IO_APIC_irq,
1505 .ack = ack_apic_edge,
1506 .eoi = ack_apic_level,
1508 .set_affinity = set_ioapic_affinity_irq,
1510 .retrigger = ioapic_retrigger_irq,
1513 static inline void init_IO_APIC_traps(void)
1518 * NOTE! The local APIC isn't very good at handling
1519 * multiple interrupts at the same interrupt level.
1520 * As the interrupt level is determined by taking the
1521 * vector number and shifting that right by 4, we
1522 * want to spread these out a bit so that they don't
1523 * all fall in the same interrupt level.
1525 * Also, we've got to be careful not to trash gate
1526 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1528 for (irq = 0; irq < NR_IRQS ; irq++) {
1529 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1531 * Hmm.. We don't have an entry for this,
1532 * so default to an old-fashioned 8259
1533 * interrupt if we can..
1536 make_8259A_irq(irq);
1538 /* Strange. Oh, well.. */
1539 irq_desc[irq].chip = &no_irq_chip;
1544 static void enable_lapic_irq (unsigned int irq)
1548 v = apic_read(APIC_LVT0);
1549 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1552 static void disable_lapic_irq (unsigned int irq)
1556 v = apic_read(APIC_LVT0);
1557 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1560 static void ack_lapic_irq (unsigned int irq)
1565 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1567 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1568 .name = "local-APIC",
1569 .typename = "local-APIC-edge",
1570 .startup = NULL, /* startup_irq() not used for IRQ0 */
1571 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1572 .enable = enable_lapic_irq,
1573 .disable = disable_lapic_irq,
1574 .ack = ack_lapic_irq,
1575 .end = end_lapic_irq,
1578 static void __init setup_nmi(void)
1581 * Dirty trick to enable the NMI watchdog ...
1582 * We put the 8259A master into AEOI mode and
1583 * unmask on all local APICs LVT0 as NMI.
1585 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1586 * is from Maciej W. Rozycki - so we do not have to EOI from
1587 * the NMI handler or the timer interrupt.
1589 printk(KERN_INFO "activating NMI Watchdog ...");
1591 enable_NMI_through_LVT0();
1597 * This looks a bit hackish but it's about the only one way of sending
1598 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1599 * not support the ExtINT mode, unfortunately. We need to send these
1600 * cycles as some i82489DX-based boards have glue logic that keeps the
1601 * 8259A interrupt line asserted until INTA. --macro
1603 static inline void __init unlock_ExtINT_logic(void)
1606 struct IO_APIC_route_entry entry0, entry1;
1607 unsigned char save_control, save_freq_select;
1609 pin = find_isa_irq_pin(8, mp_INT);
1610 apic = find_isa_irq_apic(8, mp_INT);
1614 entry0 = ioapic_read_entry(apic, pin);
1616 clear_IO_APIC_pin(apic, pin);
1618 memset(&entry1, 0, sizeof(entry1));
1620 entry1.dest_mode = 0; /* physical delivery */
1621 entry1.mask = 0; /* unmask IRQ now */
1622 entry1.dest = hard_smp_processor_id();
1623 entry1.delivery_mode = dest_ExtINT;
1624 entry1.polarity = entry0.polarity;
1628 ioapic_write_entry(apic, pin, entry1);
1630 save_control = CMOS_READ(RTC_CONTROL);
1631 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1632 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1634 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1639 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1643 CMOS_WRITE(save_control, RTC_CONTROL);
1644 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1645 clear_IO_APIC_pin(apic, pin);
1647 ioapic_write_entry(apic, pin, entry0);
1651 * This code may look a bit paranoid, but it's supposed to cooperate with
1652 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1653 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1654 * fanatically on his truly buggy board.
1656 * FIXME: really need to revamp this for modern platforms only.
1658 static inline void __init check_timer(void)
1660 struct irq_cfg *cfg = irq_cfg + 0;
1661 int apic1, pin1, apic2, pin2;
1662 unsigned long flags;
1665 local_irq_save(flags);
1668 * get/set the timer IRQ vector:
1670 disable_8259A_irq(0);
1671 assign_irq_vector(0, TARGET_CPUS);
1674 * As IRQ0 is to be enabled in the 8259A, the virtual
1675 * wire has to be disabled in the local APIC.
1677 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1680 pin1 = find_isa_irq_pin(0, mp_INT);
1681 apic1 = find_isa_irq_apic(0, mp_INT);
1682 pin2 = ioapic_i8259.pin;
1683 apic2 = ioapic_i8259.apic;
1685 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1686 cfg->vector, apic1, pin1, apic2, pin2);
1689 * Some BIOS writers are clueless and report the ExtINTA
1690 * I/O APIC input from the cascaded 8259A as the timer
1691 * interrupt input. So just in case, if only one pin
1692 * was found above, try it both directly and through the
1699 } else if (pin2 == -1) {
1704 replace_pin_at_irq(0, 0, 0, apic1, pin1);
1707 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1711 * Ok, does IRQ0 through the IOAPIC work?
1714 add_pin_to_irq(0, apic1, pin1);
1715 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1717 unmask_IO_APIC_irq(0);
1718 if (!no_timer_check && timer_irq_works()) {
1719 nmi_watchdog_default();
1720 if (nmi_watchdog == NMI_IO_APIC) {
1722 enable_8259A_irq(0);
1724 if (disable_timer_pin_1 > 0)
1725 clear_IO_APIC_pin(0, pin1);
1728 clear_IO_APIC_pin(apic1, pin1);
1730 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
1731 "8254 timer not connected to IO-APIC\n");
1733 apic_printk(APIC_VERBOSE,KERN_INFO
1734 "...trying to set up timer (IRQ0) "
1735 "through the 8259A ... ");
1736 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1739 * legacy devices should be connected to IO APIC #0
1741 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1742 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1743 unmask_IO_APIC_irq(0);
1744 enable_8259A_irq(0);
1745 if (timer_irq_works()) {
1746 apic_printk(APIC_VERBOSE," works.\n");
1747 timer_through_8259 = 1;
1748 nmi_watchdog_default();
1749 if (nmi_watchdog == NMI_IO_APIC) {
1750 disable_8259A_irq(0);
1752 enable_8259A_irq(0);
1757 * Cleanup, just in case ...
1759 disable_8259A_irq(0);
1760 clear_IO_APIC_pin(apic2, pin2);
1761 apic_printk(APIC_VERBOSE," failed.\n");
1764 if (nmi_watchdog == NMI_IO_APIC) {
1765 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1766 nmi_watchdog = NMI_NONE;
1769 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1771 irq_desc[0].chip = &lapic_irq_type;
1772 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1773 enable_8259A_irq(0);
1775 if (timer_irq_works()) {
1776 apic_printk(APIC_VERBOSE," works.\n");
1779 disable_8259A_irq(0);
1780 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1781 apic_printk(APIC_VERBOSE," failed.\n");
1783 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1787 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1789 unlock_ExtINT_logic();
1791 if (timer_irq_works()) {
1792 apic_printk(APIC_VERBOSE," works.\n");
1795 apic_printk(APIC_VERBOSE," failed :(.\n");
1796 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1798 local_irq_restore(flags);
1801 static int __init notimercheck(char *s)
1806 __setup("no_timer_check", notimercheck);
1810 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1811 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1812 * Linux doesn't really care, as it's not actually used
1813 * for any interrupt handling anyway.
1815 #define PIC_IRQS (1<<2)
1817 void __init setup_IO_APIC(void)
1821 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1825 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1827 io_apic_irqs = ~PIC_IRQS;
1829 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1832 setup_IO_APIC_irqs();
1833 init_IO_APIC_traps();
1839 struct sysfs_ioapic_data {
1840 struct sys_device dev;
1841 struct IO_APIC_route_entry entry[0];
1843 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1845 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1847 struct IO_APIC_route_entry *entry;
1848 struct sysfs_ioapic_data *data;
1851 data = container_of(dev, struct sysfs_ioapic_data, dev);
1852 entry = data->entry;
1853 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1854 *entry = ioapic_read_entry(dev->id, i);
1859 static int ioapic_resume(struct sys_device *dev)
1861 struct IO_APIC_route_entry *entry;
1862 struct sysfs_ioapic_data *data;
1863 unsigned long flags;
1864 union IO_APIC_reg_00 reg_00;
1867 data = container_of(dev, struct sysfs_ioapic_data, dev);
1868 entry = data->entry;
1870 spin_lock_irqsave(&ioapic_lock, flags);
1871 reg_00.raw = io_apic_read(dev->id, 0);
1872 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1873 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1874 io_apic_write(dev->id, 0, reg_00.raw);
1876 spin_unlock_irqrestore(&ioapic_lock, flags);
1877 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1878 ioapic_write_entry(dev->id, i, entry[i]);
1883 static struct sysdev_class ioapic_sysdev_class = {
1885 .suspend = ioapic_suspend,
1886 .resume = ioapic_resume,
1889 static int __init ioapic_init_sysfs(void)
1891 struct sys_device * dev;
1894 error = sysdev_class_register(&ioapic_sysdev_class);
1898 for (i = 0; i < nr_ioapics; i++ ) {
1899 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1900 * sizeof(struct IO_APIC_route_entry);
1901 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1902 if (!mp_ioapic_data[i]) {
1903 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1906 dev = &mp_ioapic_data[i]->dev;
1908 dev->cls = &ioapic_sysdev_class;
1909 error = sysdev_register(dev);
1911 kfree(mp_ioapic_data[i]);
1912 mp_ioapic_data[i] = NULL;
1913 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1921 device_initcall(ioapic_init_sysfs);
1924 * Dynamic irq allocate and deallocation
1926 int create_irq(void)
1928 /* Allocate an unused irq */
1931 unsigned long flags;
1934 spin_lock_irqsave(&vector_lock, flags);
1935 for (new = (NR_IRQS - 1); new >= 0; new--) {
1936 if (platform_legacy_irq(new))
1938 if (irq_cfg[new].vector != 0)
1940 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1944 spin_unlock_irqrestore(&vector_lock, flags);
1947 dynamic_irq_init(irq);
1952 void destroy_irq(unsigned int irq)
1954 unsigned long flags;
1956 dynamic_irq_cleanup(irq);
1958 spin_lock_irqsave(&vector_lock, flags);
1959 __clear_irq_vector(irq);
1960 spin_unlock_irqrestore(&vector_lock, flags);
1964 * MSI message composition
1966 #ifdef CONFIG_PCI_MSI
1967 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1969 struct irq_cfg *cfg = irq_cfg + irq;
1975 err = assign_irq_vector(irq, tmp);
1977 cpus_and(tmp, cfg->domain, tmp);
1978 dest = cpu_mask_to_apicid(tmp);
1980 msg->address_hi = MSI_ADDR_BASE_HI;
1983 ((INT_DEST_MODE == 0) ?
1984 MSI_ADDR_DEST_MODE_PHYSICAL:
1985 MSI_ADDR_DEST_MODE_LOGICAL) |
1986 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1987 MSI_ADDR_REDIRECTION_CPU:
1988 MSI_ADDR_REDIRECTION_LOWPRI) |
1989 MSI_ADDR_DEST_ID(dest);
1992 MSI_DATA_TRIGGER_EDGE |
1993 MSI_DATA_LEVEL_ASSERT |
1994 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1995 MSI_DATA_DELIVERY_FIXED:
1996 MSI_DATA_DELIVERY_LOWPRI) |
1997 MSI_DATA_VECTOR(cfg->vector);
2003 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2005 struct irq_cfg *cfg = irq_cfg + irq;
2010 cpus_and(tmp, mask, cpu_online_map);
2011 if (cpus_empty(tmp))
2014 if (assign_irq_vector(irq, mask))
2017 cpus_and(tmp, cfg->domain, mask);
2018 dest = cpu_mask_to_apicid(tmp);
2020 read_msi_msg(irq, &msg);
2022 msg.data &= ~MSI_DATA_VECTOR_MASK;
2023 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2024 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2025 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2027 write_msi_msg(irq, &msg);
2028 irq_desc[irq].affinity = mask;
2030 #endif /* CONFIG_SMP */
2033 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2034 * which implement the MSI or MSI-X Capability Structure.
2036 static struct irq_chip msi_chip = {
2038 .unmask = unmask_msi_irq,
2039 .mask = mask_msi_irq,
2040 .ack = ack_apic_edge,
2042 .set_affinity = set_msi_irq_affinity,
2044 .retrigger = ioapic_retrigger_irq,
2047 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2055 ret = msi_compose_msg(dev, irq, &msg);
2061 set_irq_msi(irq, desc);
2062 write_msi_msg(irq, &msg);
2064 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2069 void arch_teardown_msi_irq(unsigned int irq)
2076 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2078 struct irq_cfg *cfg = irq_cfg + irq;
2083 cpus_and(tmp, mask, cpu_online_map);
2084 if (cpus_empty(tmp))
2087 if (assign_irq_vector(irq, mask))
2090 cpus_and(tmp, cfg->domain, mask);
2091 dest = cpu_mask_to_apicid(tmp);
2093 dmar_msi_read(irq, &msg);
2095 msg.data &= ~MSI_DATA_VECTOR_MASK;
2096 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2097 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2098 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2100 dmar_msi_write(irq, &msg);
2101 irq_desc[irq].affinity = mask;
2103 #endif /* CONFIG_SMP */
2105 struct irq_chip dmar_msi_type = {
2107 .unmask = dmar_msi_unmask,
2108 .mask = dmar_msi_mask,
2109 .ack = ack_apic_edge,
2111 .set_affinity = dmar_msi_set_affinity,
2113 .retrigger = ioapic_retrigger_irq,
2116 int arch_setup_dmar_msi(unsigned int irq)
2121 ret = msi_compose_msg(NULL, irq, &msg);
2124 dmar_msi_write(irq, &msg);
2125 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2131 #endif /* CONFIG_PCI_MSI */
2133 * Hypertransport interrupt support
2135 #ifdef CONFIG_HT_IRQ
2139 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2141 struct ht_irq_msg msg;
2142 fetch_ht_irq_msg(irq, &msg);
2144 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2145 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2147 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2148 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2150 write_ht_irq_msg(irq, &msg);
2153 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2155 struct irq_cfg *cfg = irq_cfg + irq;
2159 cpus_and(tmp, mask, cpu_online_map);
2160 if (cpus_empty(tmp))
2163 if (assign_irq_vector(irq, mask))
2166 cpus_and(tmp, cfg->domain, mask);
2167 dest = cpu_mask_to_apicid(tmp);
2169 target_ht_irq(irq, dest, cfg->vector);
2170 irq_desc[irq].affinity = mask;
2174 static struct irq_chip ht_irq_chip = {
2176 .mask = mask_ht_irq,
2177 .unmask = unmask_ht_irq,
2178 .ack = ack_apic_edge,
2180 .set_affinity = set_ht_irq_affinity,
2182 .retrigger = ioapic_retrigger_irq,
2185 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2187 struct irq_cfg *cfg = irq_cfg + irq;
2192 err = assign_irq_vector(irq, tmp);
2194 struct ht_irq_msg msg;
2197 cpus_and(tmp, cfg->domain, tmp);
2198 dest = cpu_mask_to_apicid(tmp);
2200 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2204 HT_IRQ_LOW_DEST_ID(dest) |
2205 HT_IRQ_LOW_VECTOR(cfg->vector) |
2206 ((INT_DEST_MODE == 0) ?
2207 HT_IRQ_LOW_DM_PHYSICAL :
2208 HT_IRQ_LOW_DM_LOGICAL) |
2209 HT_IRQ_LOW_RQEOI_EDGE |
2210 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2211 HT_IRQ_LOW_MT_FIXED :
2212 HT_IRQ_LOW_MT_ARBITRATED) |
2213 HT_IRQ_LOW_IRQ_MASKED;
2215 write_ht_irq_msg(irq, &msg);
2217 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2218 handle_edge_irq, "edge");
2222 #endif /* CONFIG_HT_IRQ */
2224 /* --------------------------------------------------------------------------
2225 ACPI-based IOAPIC Configuration
2226 -------------------------------------------------------------------------- */
2230 #define IO_APIC_MAX_ID 0xFE
2232 int __init io_apic_get_redir_entries (int ioapic)
2234 union IO_APIC_reg_01 reg_01;
2235 unsigned long flags;
2237 spin_lock_irqsave(&ioapic_lock, flags);
2238 reg_01.raw = io_apic_read(ioapic, 1);
2239 spin_unlock_irqrestore(&ioapic_lock, flags);
2241 return reg_01.bits.entries;
2245 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2247 if (!IO_APIC_IRQ(irq)) {
2248 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2254 * IRQs < 16 are already in the irq_2_pin[] map
2257 add_pin_to_irq(irq, ioapic, pin);
2259 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2265 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2269 if (skip_ioapic_setup)
2272 for (i = 0; i < mp_irq_entries; i++)
2273 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2274 mp_irqs[i].mpc_srcbusirq == bus_irq)
2276 if (i >= mp_irq_entries)
2279 *trigger = irq_trigger(i);
2280 *polarity = irq_polarity(i);
2284 #endif /* CONFIG_ACPI */
2287 * This function currently is only a helper for the i386 smp boot process where
2288 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2289 * so mask in all cases should simply be TARGET_CPUS
2292 void __init setup_ioapic_dest(void)
2294 int pin, ioapic, irq, irq_entry;
2296 if (skip_ioapic_setup == 1)
2299 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2300 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2301 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2302 if (irq_entry == -1)
2304 irq = pin_2_irq(irq_entry, ioapic, pin);
2306 /* setup_IO_APIC_irqs could fail to get vector for some device
2307 * when you have too many devices, because at that time only boot
2310 if (!irq_cfg[irq].vector)
2311 setup_IO_APIC_irq(ioapic, pin, irq,
2312 irq_trigger(irq_entry),
2313 irq_polarity(irq_entry));
2315 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2322 #define IOAPIC_RESOURCE_NAME_SIZE 11
2324 static struct resource *ioapic_resources;
2326 static struct resource * __init ioapic_setup_resources(void)
2329 struct resource *res;
2333 if (nr_ioapics <= 0)
2336 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2339 mem = alloc_bootmem(n);
2343 mem += sizeof(struct resource) * nr_ioapics;
2345 for (i = 0; i < nr_ioapics; i++) {
2347 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2348 sprintf(mem, "IOAPIC %u", i);
2349 mem += IOAPIC_RESOURCE_NAME_SIZE;
2353 ioapic_resources = res;
2358 void __init ioapic_init_mappings(void)
2360 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2361 struct resource *ioapic_res;
2364 ioapic_res = ioapic_setup_resources();
2365 for (i = 0; i < nr_ioapics; i++) {
2366 if (smp_found_config) {
2367 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2369 ioapic_phys = (unsigned long)
2370 alloc_bootmem_pages(PAGE_SIZE);
2371 ioapic_phys = __pa(ioapic_phys);
2373 set_fixmap_nocache(idx, ioapic_phys);
2374 apic_printk(APIC_VERBOSE,
2375 "mapped IOAPIC to %016lx (%016lx)\n",
2376 __fix_to_virt(idx), ioapic_phys);
2379 if (ioapic_res != NULL) {
2380 ioapic_res->start = ioapic_phys;
2381 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2387 static int __init ioapic_insert_resources(void)
2390 struct resource *r = ioapic_resources;
2394 "IO APIC resources could be not be allocated.\n");
2398 for (i = 0; i < nr_ioapics; i++) {
2399 insert_resource(&iomem_resource, r);
2406 /* Insert the IO APIC resources after PCI initialization has occured to handle
2407 * IO APICS that are mapped in on a BAR in PCI space. */
2408 late_initcall(ioapic_insert_resources);