arch/x86/cpu/intel_common/p2sb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Primary-to-Sideband Bridge
   4  *
   5  * Copyright 2019 Google LLC
   6  */
   7
   8 #define LOG_CATEGORY UCLASS_P2SB
   9
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <log.h>
  13 #include <p2sb.h>
  14 #include <spl.h>
  15 #include <asm/p2sb.h>
  16 #include <asm/pci.h>
  17 #include <linux/bitops.h>
  18
  19 #define PCH_P2SB_E0             0xe0
  20 #define HIDE_BIT                BIT(0)
  21
  22 /* PCI config space registers */
  23 #define HPTC_OFFSET             0x60
  24 #define HPTC_ADDR_ENABLE_BIT    BIT(7)
  25
  26 /* High Performance Event Timer Configuration */
  27 #define P2SB_HPTC                               0x60
  28 #define P2SB_HPTC_ADDRESS_ENABLE                BIT(7)
  29
  30 /*
  31  * ADDRESS_SELECT            ENCODING_RANGE
  32  *      0                 0xfed0 0000 - 0xfed0 03ff
  33  *      1                 0xfed0 1000 - 0xfed0 13ff
  34  *      2                 0xfed0 2000 - 0xfed0 23ff
  35  *      3                 0xfed0 3000 - 0xfed0 33ff
  36  */
  37 #define P2SB_HPTC_ADDRESS_SELECT_0              (0 << 0)
  38 #define P2SB_HPTC_ADDRESS_SELECT_1              (1 << 0)
  39 #define P2SB_HPTC_ADDRESS_SELECT_2              (2 << 0)
  40 #define P2SB_HPTC_ADDRESS_SELECT_3              (3 << 0)
  41
  42 /*
  43  * p2sb_early_init() - Enable decoding for HPET range
  44  *
  45  * This is needed by FSP-M which uses the High Precision Event Timer.
  46  *
  47  * @dev: P2SB device
  48  * Return: 0 if OK, -ve on error
  49  */
  50 static int p2sb_early_init(struct udevice *dev)
  51 {
  52         struct p2sb_plat *plat = dev_get_plat(dev);
  53         pci_dev_t pdev = plat->bdf;
  54
  55         /*
  56          * Enable decoding for HPET memory address range.
  57          * HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
  58          * the High Performance Timer memory address range
  59          * selected by bits 1:0
  60          */
  61         pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
  62                              PCI_SIZE_8);
  63
  64         /* Enable PCR Base address in PCH */
  65         pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
  66                              PCI_SIZE_32);
  67         pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
  68
  69         /* Enable P2SB MSE */
  70         pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
  71                              PCI_COMMAND_MEMORY, PCI_SIZE_8);
  72
  73         return 0;
  74 }
  75
  76 static int p2sb_spl_init(struct udevice *dev)
  77 {
  78         /* Enable decoding for HPET. Needed for FSP global pointer storage */
  79         dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
  80                             P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
  81
  82         return 0;
  83 }
  84
  85 int p2sb_of_to_plat(struct udevice *dev)
  86 {
  87         struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
  88         struct p2sb_plat *plat = dev_get_plat(dev);
  89
  90 #if CONFIG_IS_ENABLED(OF_REAL)
  91         int ret;
  92         u32 base[2];
  93
  94         ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
  95         if (ret)
  96                 return log_msg_ret("Missing/short early-regs", ret);
  97         plat->mmio_base = base[0];
  98         /* TPL sets up the initial BAR */
  99         if (spl_phase() == PHASE_TPL) {
 100                 plat->bdf = pci_get_devfn(dev);
 101                 if (plat->bdf < 0)
 102                         return log_msg_ret("Cannot get p2sb PCI address",
 103                                            plat->bdf);
 104         }
 105         upriv->mmio_base = plat->mmio_base;
 106 #else
 107         plat->mmio_base = plat->dtplat.early_regs[0];
 108         plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
 109         upriv->mmio_base = plat->mmio_base;
 110 #endif
 111
 112         return 0;
 113 }
 114
 115 static int p2sb_probe(struct udevice *dev)
 116 {
 117         if (spl_phase() == PHASE_TPL)
 118                 return p2sb_early_init(dev);
 119         else if (spl_phase() == PHASE_SPL)
 120                 return p2sb_spl_init(dev);
 121
 122         return 0;
 123 }
 124
 125 static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
 126 {
 127         dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
 128                               hide ? HIDE_BIT : 0);
 129 }
 130
 131 static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
 132 {
 133         u16 vendor;
 134
 135         if (!CONFIG_IS_ENABLED(PCI))
 136                 return -EPERM;
 137         p2sb_set_hide_bit(dev, hide);
 138
 139         dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
 140         if (hide && vendor != 0xffff)
 141                 return log_msg_ret("hide", -EEXIST);
 142         else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
 143                 return log_msg_ret("unhide", -ENOMEDIUM);
 144
 145         return 0;
 146 }
 147
 148 static int p2sb_remove(struct udevice *dev)
 149 {
 150         int ret;
 151
 152         ret = intel_p2sb_set_hide(dev, true);
 153         if (ret)
 154                 return log_msg_ret("hide", ret);
 155
 156         return 0;
 157 }
 158
 159 static int p2sb_child_post_bind(struct udevice *dev)
 160 {
 161         if (CONFIG_IS_ENABLED(OF_REAL)) {
 162                 struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
 163                 int ret;
 164                 u32 pid;
 165
 166                 ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
 167                 if (ret)
 168                         return ret;
 169                 pplat->pid = pid;
 170         }
 171
 172         return 0;
 173 }
 174
 175 static const struct p2sb_ops p2sb_ops = {
 176         .set_hide       = intel_p2sb_set_hide,
 177 };
 178
 179 #if CONFIG_IS_ENABLED(OF_REAL)
 180 static const struct udevice_id p2sb_ids[] = {
 181         { .compatible = "intel,p2sb" },
 182         { }
 183 };
 184 #endif
 185
 186 U_BOOT_DRIVER(intel_p2sb) = {
 187         .name           = "intel_p2sb",
 188         .id             = UCLASS_P2SB,
 189         .of_match       = of_match_ptr(p2sb_ids),
 190         .probe          = p2sb_probe,
 191         .remove         = p2sb_remove,
 192         .ops            = &p2sb_ops,
 193         .of_to_plat = p2sb_of_to_plat,
 194         .plat_auto      = sizeof(struct p2sb_plat),
 195         .per_child_plat_auto    = sizeof(struct p2sb_child_plat),
 196         .child_post_bind = p2sb_child_post_bind,
 197         .flags          = DM_FLAG_OS_PREPARE,
 198 };