arch/riscv/include/asm/csr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2015 Regents of the University of California
   4  *
   5  * Taken from Linux arch/riscv/include/asm/csr.h
   6  */
   7
   8 #ifndef _ASM_RISCV_CSR_H
   9 #define _ASM_RISCV_CSR_H
  10
  11 #include <linux/const.h>
  12
  13 /* Status register flags */
  14 #define SR_SIE          _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
  15 #define SR_SPIE         _AC(0x00000020, UL) /* Previous Supervisor IE */
  16 #define SR_SPP          _AC(0x00000100, UL) /* Previously Supervisor */
  17 #define SR_SUM          _AC(0x00040000, UL) /* Supervisor access User Memory */
  18
  19 #define SR_FS           _AC(0x00006000, UL) /* Floating-point Status */
  20 #define SR_FS_OFF       _AC(0x00000000, UL)
  21 #define SR_FS_INITIAL   _AC(0x00002000, UL)
  22 #define SR_FS_CLEAN     _AC(0x00004000, UL)
  23 #define SR_FS_DIRTY     _AC(0x00006000, UL)
  24
  25 #define SR_XS           _AC(0x00018000, UL) /* Extension Status */
  26 #define SR_XS_OFF       _AC(0x00000000, UL)
  27 #define SR_XS_INITIAL   _AC(0x00008000, UL)
  28 #define SR_XS_CLEAN     _AC(0x00010000, UL)
  29 #define SR_XS_DIRTY     _AC(0x00018000, UL)
  30
  31 #ifndef CONFIG_64BIT
  32 #define SR_SD           _AC(0x80000000, UL) /* FS/XS dirty */
  33 #else
  34 #define SR_SD           _AC(0x8000000000000000, UL) /* FS/XS dirty */
  35 #endif
  36
  37 /* SATP flags */
  38 #if __riscv_xlen == 32
  39 #define SATP_PPN        _AC(0x003FFFFF, UL)
  40 #define SATP_MODE_32    _AC(0x80000000, UL)
  41 #define SATP_MODE       SATP_MODE_32
  42 #else
  43 #define SATP_PPN        _AC(0x00000FFFFFFFFFFF, UL)
  44 #define SATP_MODE_39    _AC(0x8000000000000000, UL)
  45 #define SATP_MODE       SATP_MODE_39
  46 #endif
  47
  48 /* Interrupt Enable and Interrupt Pending flags */
  49 #define SIE_SSIE        _AC(0x00000002, UL) /* Software Interrupt Enable */
  50 #define SIE_STIE        _AC(0x00000020, UL) /* Timer Interrupt Enable */
  51
  52 #define EXC_INST_MISALIGNED     0
  53 #define EXC_INST_ACCESS         1
  54 #define EXC_BREAKPOINT          3
  55 #define EXC_LOAD_ACCESS         5
  56 #define EXC_STORE_ACCESS        7
  57 #define EXC_SYSCALL             8
  58 #define EXC_INST_PAGE_FAULT     12
  59 #define EXC_LOAD_PAGE_FAULT     13
  60 #define EXC_STORE_PAGE_FAULT    15
  61
  62 #ifndef __ASSEMBLY__
  63
  64 #define xcsr(csr)       #csr
  65
  66 #define csr_swap(csr, val)                                      \
  67 ({                                                              \
  68         unsigned long __v = (unsigned long)(val);               \
  69         __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1"     \
  70                               : "=r" (__v) : "rK" (__v)         \
  71                               : "memory");                      \
  72         __v;                                                    \
  73 })
  74
  75 #define csr_read(csr)                                           \
  76 ({                                                              \
  77         register unsigned long __v;                             \
  78         __asm__ __volatile__ ("csrr %0, " xcsr(csr)             \
  79                               : "=r" (__v) :                    \
  80                               : "memory");                      \
  81         __v;                                                    \
  82 })
  83
  84 #define csr_write(csr, val)                                     \
  85 ({                                                              \
  86         unsigned long __v = (unsigned long)(val);               \
  87         __asm__ __volatile__ ("csrw " xcsr(csr) ", %0"          \
  88                               : : "rK" (__v)                    \
  89                               : "memory");                      \
  90 })
  91
  92 #define csr_read_set(csr, val)                                  \
  93 ({                                                              \
  94         unsigned long __v = (unsigned long)(val);               \
  95         __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1"     \
  96                               : "=r" (__v) : "rK" (__v)         \
  97                               : "memory");                      \
  98         __v;                                                    \
  99 })
 100
 101 #define csr_set(csr, val)                                       \
 102 ({                                                              \
 103         unsigned long __v = (unsigned long)(val);               \
 104         __asm__ __volatile__ ("csrs " xcsr(csr) ", %0"          \
 105                               : : "rK" (__v)                    \
 106                               : "memory");                      \
 107 })
 108
 109 #define csr_read_clear(csr, val)                                \
 110 ({                                                              \
 111         unsigned long __v = (unsigned long)(val);               \
 112         __asm__ __volatile__ ("csrrc %0, " xcsr(csr) ", %1"     \
 113                               : "=r" (__v) : "rK" (__v)         \
 114                               : "memory");                      \
 115         __v;                                                    \
 116 })
 117
 118 #define csr_clear(csr, val)                                     \
 119 ({                                                              \
 120         unsigned long __v = (unsigned long)(val);               \
 121         __asm__ __volatile__ ("csrc " xcsr(csr) ", %0"          \
 122                               : : "rK" (__v)                    \
 123                               : "memory");                      \
 124 })
 125
 126 #endif /* __ASSEMBLY__ */
 127
 128 #endif /* _ASM_RISCV_CSR_H */