1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
12 /* AHB0 BUS Devices */
13 #define DDRC_BASE 0xb3010000
15 /* AHB2 BUS Devices */
16 #define NEMC_BASE 0xb3410000
17 #define BCH_BASE 0xb34d0000
20 #define CPM_BASE 0xb0000000
21 #define TCU_BASE 0xb0002000
22 #define WDT_BASE 0xb0002000
23 #define GPIO_BASE 0xb0010000
24 #define UART0_BASE 0xb0030000
25 #define UART1_BASE 0xb0031000
26 #define UART2_BASE 0xb0032000
27 #define UART3_BASE 0xb0033000
28 #define MSC0_BASE 0xb3450000
29 #define MSC1_BASE 0xb3460000
30 #define MSC2_BASE 0xb3470000
36 #define GPIO_PXPIN(n) (0x00 + (n) * 0x100)
37 #define GPIO_PXINT(n) (0x10 + (n) * 0x100)
38 #define GPIO_PXINTS(n) (0x14 + (n) * 0x100)
39 #define GPIO_PXINTC(n) (0x18 + (n) * 0x100)
40 #define GPIO_PXMASK(n) (0x20 + (n) * 0x100)
41 #define GPIO_PXMASKS(n) (0x24 + (n) * 0x100)
42 #define GPIO_PXMASKC(n) (0x28 + (n) * 0x100)
43 #define GPIO_PXPAT1(n) (0x30 + (n) * 0x100)
44 #define GPIO_PXPAT1S(n) (0x34 + (n) * 0x100)
45 #define GPIO_PXPAT1C(n) (0x38 + (n) * 0x100)
46 #define GPIO_PXPAT0(n) (0x40 + (n) * 0x100)
47 #define GPIO_PXPAT0S(n) (0x44 + (n) * 0x100)
48 #define GPIO_PXPAT0C(n) (0x48 + (n) * 0x100)
49 #define GPIO_PXFLG(n) (0x50 + (n) * 0x100)
50 #define GPIO_PXFLGC(n) (0x54 + (n) * 0x100)
51 #define GPIO_PXOEN(n) (0x60 + (n) * 0x100)
52 #define GPIO_PXOENS(n) (0x64 + (n) * 0x100)
53 #define GPIO_PXOENC(n) (0x68 + (n) * 0x100)
54 #define GPIO_PXPEN(n) (0x70 + (n) * 0x100)
55 #define GPIO_PXPENS(n) (0x74 + (n) * 0x100)
56 #define GPIO_PXPENC(n) (0x78 + (n) * 0x100)
57 #define GPIO_PXDS(n) (0x80 + (n) * 0x100)
58 #define GPIO_PXDSS(n) (0x84 + (n) * 0x100)
59 #define GPIO_PXDSC(n) (0x88 + (n) * 0x100)
62 #define JZ4780_SYS_EXTAL 48000000
63 #define JZ4780_SYS_MEM_SPEED (CONFIG_SYS_MHZ * 1000000)
64 #define JZ4780_SYS_MEM_DIV 3
65 #define JZ4780_SYS_AUDIO_SPEED (768 * 1000000)
67 #define JZ4780_APLL_M 1
68 #define JZ4780_APLL_N 1
69 #define JZ4780_APLL_OD 1
71 #define JZ4780_MPLL_M (JZ4780_SYS_MEM_SPEED / JZ4780_SYS_EXTAL * 2)
72 #define JZ4780_MPLL_N 2
73 #define JZ4780_MPLL_OD 1
75 #define JZ4780_EPLL_M (JZ4780_SYS_AUDIO_SPEED * 2 / JZ4780_SYS_EXTAL)
76 #define JZ4780_EPLL_N 1
77 #define JZ4780_EPLL_OD 2
79 #define JZ4780_VPLL_M ((888 * 1000000) * 2 / JZ4780_SYS_EXTAL)
80 #define JZ4780_VPLL_N 1
81 #define JZ4780_VPLL_OD 2
85 u32 sdram_size(int bank);
87 const u32 jz4780_clk_get_efuse_clk(void);
88 void jz4780_clk_ungate_ethernet(void);
89 void jz4780_clk_ungate_mmc(void);
90 void jz4780_clk_ungate_uart(const unsigned int uart);
92 void jz4780_efuse_read(size_t addr, size_t count, u8 *buf);
93 void jz4780_efuse_init(u32 ahb2_rate);
95 void jz4780_tcu_wdt_start(void);
97 #ifdef CONFIG_SPL_BUILD
98 int jz_mmc_init(void __iomem *base);
101 #endif /* __ASSEMBLY__ */
103 #endif /* __JZ4780_H__ */