arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <plat/dma.h>
  28 #include <plat/mcbsp.h>
  29
  30 #include "../mach-omap2/cm-regbits-34xx.h"
  31
  32 struct omap_mcbsp **mcbsp_ptr;
  33 int omap_mcbsp_count, omap_mcbsp_cache_size;
  34
  35 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  36 {
  37         if (cpu_class_is_omap1()) {
  38                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
  39                 __raw_writew((u16)val, mcbsp->io_base + reg);
  40         } else if (cpu_is_omap2420()) {
  41                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
  42                 __raw_writew((u16)val, mcbsp->io_base + reg);
  43         } else {
  44                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
  45                 __raw_writel(val, mcbsp->io_base + reg);
  46         }
  47 }
  48
  49 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  50 {
  51         if (cpu_class_is_omap1()) {
  52                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  53                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
  54         } else if (cpu_is_omap2420()) {
  55                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  56                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  57         } else {
  58                 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
  59                                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  60         }
  61 }
  62
  63 #ifdef CONFIG_ARCH_OMAP3
  64 void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  65 {
  66         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  67 }
  68
  69 int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  70 {
  71         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  72 }
  73 #endif
  74
  75 #define MCBSP_READ(mcbsp, reg) \
  76                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  77 #define MCBSP_WRITE(mcbsp, reg, val) \
  78                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  79 #define MCBSP_READ_CACHE(mcbsp, reg) \
  80                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  81
  82 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  83 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  84
  85 #define MCBSP_ST_READ(mcbsp, reg) \
  86                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  87 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  88                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  89
  90 static void omap_mcbsp_dump_reg(u8 id)
  91 {
  92         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  93
  94         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  95         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  96                         MCBSP_READ(mcbsp, DRR2));
  97         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  98                         MCBSP_READ(mcbsp, DRR1));
  99         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
 100                         MCBSP_READ(mcbsp, DXR2));
 101         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
 102                         MCBSP_READ(mcbsp, DXR1));
 103         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
 104                         MCBSP_READ(mcbsp, SPCR2));
 105         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
 106                         MCBSP_READ(mcbsp, SPCR1));
 107         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
 108                         MCBSP_READ(mcbsp, RCR2));
 109         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 110                         MCBSP_READ(mcbsp, RCR1));
 111         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 112                         MCBSP_READ(mcbsp, XCR2));
 113         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 114                         MCBSP_READ(mcbsp, XCR1));
 115         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 116                         MCBSP_READ(mcbsp, SRGR2));
 117         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 118                         MCBSP_READ(mcbsp, SRGR1));
 119         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 120                         MCBSP_READ(mcbsp, PCR0));
 121         dev_dbg(mcbsp->dev, "***********************\n");
 122 }
 123
 124 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 125 {
 126         struct omap_mcbsp *mcbsp_tx = dev_id;
 127         u16 irqst_spcr2;
 128
 129         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 130         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 131
 132         if (irqst_spcr2 & XSYNC_ERR) {
 133                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 134                         irqst_spcr2);
 135                 /* Writing zero to XSYNC_ERR clears the IRQ */
 136                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 137         } else {
 138                 complete(&mcbsp_tx->tx_irq_completion);
 139         }
 140
 141         return IRQ_HANDLED;
 142 }
 143
 144 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 145 {
 146         struct omap_mcbsp *mcbsp_rx = dev_id;
 147         u16 irqst_spcr1;
 148
 149         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 150         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 151
 152         if (irqst_spcr1 & RSYNC_ERR) {
 153                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 154                         irqst_spcr1);
 155                 /* Writing zero to RSYNC_ERR clears the IRQ */
 156                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 157         } else {
 158                 complete(&mcbsp_rx->tx_irq_completion);
 159         }
 160
 161         return IRQ_HANDLED;
 162 }
 163
 164 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 165 {
 166         struct omap_mcbsp *mcbsp_dma_tx = data;
 167
 168         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 169                 MCBSP_READ(mcbsp_dma_tx, SPCR2));
 170
 171         /* We can free the channels */
 172         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 173         mcbsp_dma_tx->dma_tx_lch = -1;
 174
 175         complete(&mcbsp_dma_tx->tx_dma_completion);
 176 }
 177
 178 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 179 {
 180         struct omap_mcbsp *mcbsp_dma_rx = data;
 181
 182         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 183                 MCBSP_READ(mcbsp_dma_rx, SPCR2));
 184
 185         /* We can free the channels */
 186         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 187         mcbsp_dma_rx->dma_rx_lch = -1;
 188
 189         complete(&mcbsp_dma_rx->rx_dma_completion);
 190 }
 191
 192 /*
 193  * omap_mcbsp_config simply write a config to the
 194  * appropriate McBSP.
 195  * You either call this function or set the McBSP registers
 196  * by yourself before calling omap_mcbsp_start().
 197  */
 198 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 199 {
 200         struct omap_mcbsp *mcbsp;
 201
 202         if (!omap_mcbsp_check_valid_id(id)) {
 203                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 204                 return;
 205         }
 206         mcbsp = id_to_mcbsp_ptr(id);
 207
 208         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 209                         mcbsp->id, mcbsp->phys_base);
 210
 211         /* We write the given config */
 212         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 213         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 214         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 215         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 216         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 217         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 218         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 219         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 220         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 221         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 222         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 223         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 224                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 225                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 226         }
 227 }
 228 EXPORT_SYMBOL(omap_mcbsp_config);
 229
 230 #ifdef CONFIG_ARCH_OMAP3
 231 static void omap_st_on(struct omap_mcbsp *mcbsp)
 232 {
 233         unsigned int w;
 234
 235         /*
 236          * Sidetone uses McBSP ICLK - which must not idle when sidetones
 237          * are enabled or sidetones start sounding ugly.
 238          */
 239         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 240         w &= ~(1 << (mcbsp->id - 2));
 241         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 242
 243         /* Enable McBSP Sidetone */
 244         w = MCBSP_READ(mcbsp, SSELCR);
 245         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 246
 247         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 248         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 249
 250         /* Enable Sidetone from Sidetone Core */
 251         w = MCBSP_ST_READ(mcbsp, SSELCR);
 252         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 253 }
 254
 255 static void omap_st_off(struct omap_mcbsp *mcbsp)
 256 {
 257         unsigned int w;
 258
 259         w = MCBSP_ST_READ(mcbsp, SSELCR);
 260         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 261
 262         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 263         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
 264
 265         w = MCBSP_READ(mcbsp, SSELCR);
 266         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 267
 268         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 269         w |= 1 << (mcbsp->id - 2);
 270         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 271 }
 272
 273 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 274 {
 275         u16 val, i;
 276
 277         val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 278         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
 279
 280         val = MCBSP_ST_READ(mcbsp, SSELCR);
 281
 282         if (val & ST_COEFFWREN)
 283                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 284
 285         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 286
 287         for (i = 0; i < 128; i++)
 288                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 289
 290         i = 0;
 291
 292         val = MCBSP_ST_READ(mcbsp, SSELCR);
 293         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 294                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 295
 296         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 297
 298         if (i == 1000)
 299                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 300 }
 301
 302 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 303 {
 304         u16 w;
 305         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 306
 307         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 308         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 309
 310         w = MCBSP_ST_READ(mcbsp, SSELCR);
 311
 312         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 313                       ST_CH1GAIN(st_data->ch1gain));
 314 }
 315
 316 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
 317 {
 318         struct omap_mcbsp *mcbsp;
 319         struct omap_mcbsp_st_data *st_data;
 320         int ret = 0;
 321
 322         if (!omap_mcbsp_check_valid_id(id)) {
 323                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 324                 return -ENODEV;
 325         }
 326
 327         mcbsp = id_to_mcbsp_ptr(id);
 328         st_data = mcbsp->st_data;
 329
 330         if (!st_data)
 331                 return -ENOENT;
 332
 333         spin_lock_irq(&mcbsp->lock);
 334         if (channel == 0)
 335                 st_data->ch0gain = chgain;
 336         else if (channel == 1)
 337                 st_data->ch1gain = chgain;
 338         else
 339                 ret = -EINVAL;
 340
 341         if (st_data->enabled)
 342                 omap_st_chgain(mcbsp);
 343         spin_unlock_irq(&mcbsp->lock);
 344
 345         return ret;
 346 }
 347 EXPORT_SYMBOL(omap_st_set_chgain);
 348
 349 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
 350 {
 351         struct omap_mcbsp *mcbsp;
 352         struct omap_mcbsp_st_data *st_data;
 353         int ret = 0;
 354
 355         if (!omap_mcbsp_check_valid_id(id)) {
 356                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 357                 return -ENODEV;
 358         }
 359
 360         mcbsp = id_to_mcbsp_ptr(id);
 361         st_data = mcbsp->st_data;
 362
 363         if (!st_data)
 364                 return -ENOENT;
 365
 366         spin_lock_irq(&mcbsp->lock);
 367         if (channel == 0)
 368                 *chgain = st_data->ch0gain;
 369         else if (channel == 1)
 370                 *chgain = st_data->ch1gain;
 371         else
 372                 ret = -EINVAL;
 373         spin_unlock_irq(&mcbsp->lock);
 374
 375         return ret;
 376 }
 377 EXPORT_SYMBOL(omap_st_get_chgain);
 378
 379 static int omap_st_start(struct omap_mcbsp *mcbsp)
 380 {
 381         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 382
 383         if (st_data && st_data->enabled && !st_data->running) {
 384                 omap_st_fir_write(mcbsp, st_data->taps);
 385                 omap_st_chgain(mcbsp);
 386
 387                 if (!mcbsp->free) {
 388                         omap_st_on(mcbsp);
 389                         st_data->running = 1;
 390                 }
 391         }
 392
 393         return 0;
 394 }
 395
 396 int omap_st_enable(unsigned int id)
 397 {
 398         struct omap_mcbsp *mcbsp;
 399         struct omap_mcbsp_st_data *st_data;
 400
 401         if (!omap_mcbsp_check_valid_id(id)) {
 402                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 403                 return -ENODEV;
 404         }
 405
 406         mcbsp = id_to_mcbsp_ptr(id);
 407         st_data = mcbsp->st_data;
 408
 409         if (!st_data)
 410                 return -ENODEV;
 411
 412         spin_lock_irq(&mcbsp->lock);
 413         st_data->enabled = 1;
 414         omap_st_start(mcbsp);
 415         spin_unlock_irq(&mcbsp->lock);
 416
 417         return 0;
 418 }
 419 EXPORT_SYMBOL(omap_st_enable);
 420
 421 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 422 {
 423         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 424
 425         if (st_data && st_data->running) {
 426                 if (!mcbsp->free) {
 427                         omap_st_off(mcbsp);
 428                         st_data->running = 0;
 429                 }
 430         }
 431
 432         return 0;
 433 }
 434
 435 int omap_st_disable(unsigned int id)
 436 {
 437         struct omap_mcbsp *mcbsp;
 438         struct omap_mcbsp_st_data *st_data;
 439         int ret = 0;
 440
 441         if (!omap_mcbsp_check_valid_id(id)) {
 442                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 443                 return -ENODEV;
 444         }
 445
 446         mcbsp = id_to_mcbsp_ptr(id);
 447         st_data = mcbsp->st_data;
 448
 449         if (!st_data)
 450                 return -ENODEV;
 451
 452         spin_lock_irq(&mcbsp->lock);
 453         omap_st_stop(mcbsp);
 454         st_data->enabled = 0;
 455         spin_unlock_irq(&mcbsp->lock);
 456
 457         return ret;
 458 }
 459 EXPORT_SYMBOL(omap_st_disable);
 460
 461 int omap_st_is_enabled(unsigned int id)
 462 {
 463         struct omap_mcbsp *mcbsp;
 464         struct omap_mcbsp_st_data *st_data;
 465
 466         if (!omap_mcbsp_check_valid_id(id)) {
 467                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 468                 return -ENODEV;
 469         }
 470
 471         mcbsp = id_to_mcbsp_ptr(id);
 472         st_data = mcbsp->st_data;
 473
 474         if (!st_data)
 475                 return -ENODEV;
 476
 477
 478         return st_data->enabled;
 479 }
 480 EXPORT_SYMBOL(omap_st_is_enabled);
 481
 482 /*
 483  * omap_mcbsp_set_tx_threshold configures how to deal
 484  * with transmit threshold. the threshold value and handler can be
 485  * configure in here.
 486  */
 487 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 488 {
 489         struct omap_mcbsp *mcbsp;
 490
 491         if (!cpu_is_omap34xx())
 492                 return;
 493
 494         if (!omap_mcbsp_check_valid_id(id)) {
 495                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 496                 return;
 497         }
 498         mcbsp = id_to_mcbsp_ptr(id);
 499
 500         MCBSP_WRITE(mcbsp, THRSH2, threshold);
 501 }
 502 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 503
 504 /*
 505  * omap_mcbsp_set_rx_threshold configures how to deal
 506  * with receive threshold. the threshold value and handler can be
 507  * configure in here.
 508  */
 509 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 510 {
 511         struct omap_mcbsp *mcbsp;
 512
 513         if (!cpu_is_omap34xx())
 514                 return;
 515
 516         if (!omap_mcbsp_check_valid_id(id)) {
 517                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 518                 return;
 519         }
 520         mcbsp = id_to_mcbsp_ptr(id);
 521
 522         MCBSP_WRITE(mcbsp, THRSH1, threshold);
 523 }
 524 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 525
 526 /*
 527  * omap_mcbsp_get_max_tx_thres just return the current configured
 528  * maximum threshold for transmission
 529  */
 530 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 531 {
 532         struct omap_mcbsp *mcbsp;
 533
 534         if (!omap_mcbsp_check_valid_id(id)) {
 535                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 536                 return -ENODEV;
 537         }
 538         mcbsp = id_to_mcbsp_ptr(id);
 539
 540         return mcbsp->max_tx_thres;
 541 }
 542 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 543
 544 /*
 545  * omap_mcbsp_get_max_rx_thres just return the current configured
 546  * maximum threshold for reception
 547  */
 548 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 549 {
 550         struct omap_mcbsp *mcbsp;
 551
 552         if (!omap_mcbsp_check_valid_id(id)) {
 553                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 554                 return -ENODEV;
 555         }
 556         mcbsp = id_to_mcbsp_ptr(id);
 557
 558         return mcbsp->max_rx_thres;
 559 }
 560 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 561
 562 #define MCBSP2_FIFO_SIZE        0x500 /* 1024 + 256 locations */
 563 #define MCBSP1345_FIFO_SIZE     0x80  /* 128 locations */
 564 /*
 565  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 566  */
 567 u16 omap_mcbsp_get_tx_delay(unsigned int id)
 568 {
 569         struct omap_mcbsp *mcbsp;
 570         u16 buffstat;
 571
 572         if (!omap_mcbsp_check_valid_id(id)) {
 573                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 574                 return -ENODEV;
 575         }
 576         mcbsp = id_to_mcbsp_ptr(id);
 577
 578         /* Returns the number of free locations in the buffer */
 579         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 580
 581         /* Number of slots are different in McBSP ports */
 582         if (mcbsp->id == 2)
 583                 return MCBSP2_FIFO_SIZE - buffstat;
 584         else
 585                 return MCBSP1345_FIFO_SIZE - buffstat;
 586 }
 587 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
 588
 589 /*
 590  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 591  * to reach the threshold value (when the DMA will be triggered to read it)
 592  */
 593 u16 omap_mcbsp_get_rx_delay(unsigned int id)
 594 {
 595         struct omap_mcbsp *mcbsp;
 596         u16 buffstat, threshold;
 597
 598         if (!omap_mcbsp_check_valid_id(id)) {
 599                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 600                 return -ENODEV;
 601         }
 602         mcbsp = id_to_mcbsp_ptr(id);
 603
 604         /* Returns the number of used locations in the buffer */
 605         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 606         /* RX threshold */
 607         threshold = MCBSP_READ(mcbsp, THRSH1);
 608
 609         /* Return the number of location till we reach the threshold limit */
 610         if (threshold <= buffstat)
 611                 return 0;
 612         else
 613                 return threshold - buffstat;
 614 }
 615 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
 616
 617 /*
 618  * omap_mcbsp_get_dma_op_mode just return the current configured
 619  * operating mode for the mcbsp channel
 620  */
 621 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 622 {
 623         struct omap_mcbsp *mcbsp;
 624         int dma_op_mode;
 625
 626         if (!omap_mcbsp_check_valid_id(id)) {
 627                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 628                 return -ENODEV;
 629         }
 630         mcbsp = id_to_mcbsp_ptr(id);
 631
 632         dma_op_mode = mcbsp->dma_op_mode;
 633
 634         return dma_op_mode;
 635 }
 636 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 637
 638 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 639 {
 640         /*
 641          * Enable wakup behavior, smart idle and all wakeups
 642          * REVISIT: some wakeups may be unnecessary
 643          */
 644         if (cpu_is_omap34xx()) {
 645                 u16 syscon;
 646
 647                 syscon = MCBSP_READ(mcbsp, SYSCON);
 648                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 649
 650                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 651                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 652                                         CLOCKACTIVITY(0x02));
 653                         MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 654                 } else {
 655                         syscon |= SIDLEMODE(0x01);
 656                 }
 657
 658                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 659         }
 660 }
 661
 662 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 663 {
 664         /*
 665          * Disable wakup behavior, smart idle and all wakeups
 666          */
 667         if (cpu_is_omap34xx()) {
 668                 u16 syscon;
 669
 670                 syscon = MCBSP_READ(mcbsp, SYSCON);
 671                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 672                 /*
 673                  * HW bug workaround - If no_idle mode is taken, we need to
 674                  * go to smart_idle before going to always_idle, or the
 675                  * device will not hit retention anymore.
 676                  */
 677                 syscon |= SIDLEMODE(0x02);
 678                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 679
 680                 syscon &= ~(SIDLEMODE(0x03));
 681                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 682
 683                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 684         }
 685 }
 686 #else
 687 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 688 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 689 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 690 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 691 #endif
 692
 693 /*
 694  * We can choose between IRQ based or polled IO.
 695  * This needs to be called before omap_mcbsp_request().
 696  */
 697 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 698 {
 699         struct omap_mcbsp *mcbsp;
 700
 701         if (!omap_mcbsp_check_valid_id(id)) {
 702                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 703                 return -ENODEV;
 704         }
 705         mcbsp = id_to_mcbsp_ptr(id);
 706
 707         spin_lock(&mcbsp->lock);
 708
 709         if (!mcbsp->free) {
 710                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 711                         mcbsp->id);
 712                 spin_unlock(&mcbsp->lock);
 713                 return -EINVAL;
 714         }
 715
 716         mcbsp->io_type = io_type;
 717
 718         spin_unlock(&mcbsp->lock);
 719
 720         return 0;
 721 }
 722 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 723
 724 int omap_mcbsp_request(unsigned int id)
 725 {
 726         struct omap_mcbsp *mcbsp;
 727         void *reg_cache;
 728         int err;
 729
 730         if (!omap_mcbsp_check_valid_id(id)) {
 731                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 732                 return -ENODEV;
 733         }
 734         mcbsp = id_to_mcbsp_ptr(id);
 735
 736         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
 737         if (!reg_cache) {
 738                 return -ENOMEM;
 739         }
 740
 741         spin_lock(&mcbsp->lock);
 742         if (!mcbsp->free) {
 743                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 744                         mcbsp->id);
 745                 err = -EBUSY;
 746                 goto err_kfree;
 747         }
 748
 749         mcbsp->free = 0;
 750         mcbsp->reg_cache = reg_cache;
 751         spin_unlock(&mcbsp->lock);
 752
 753         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 754                 mcbsp->pdata->ops->request(id);
 755
 756         clk_enable(mcbsp->iclk);
 757         clk_enable(mcbsp->fclk);
 758
 759         /* Do procedure specific to omap34xx arch, if applicable */
 760         omap34xx_mcbsp_request(mcbsp);
 761
 762         /*
 763          * Make sure that transmitter, receiver and sample-rate generator are
 764          * not running before activating IRQs.
 765          */
 766         MCBSP_WRITE(mcbsp, SPCR1, 0);
 767         MCBSP_WRITE(mcbsp, SPCR2, 0);
 768
 769         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 770                 /* We need to get IRQs here */
 771                 init_completion(&mcbsp->tx_irq_completion);
 772                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 773                                         0, "McBSP", (void *)mcbsp);
 774                 if (err != 0) {
 775                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 776                                         "for McBSP%d\n", mcbsp->tx_irq,
 777                                         mcbsp->id);
 778                         goto err_clk_disable;
 779                 }
 780
 781                 init_completion(&mcbsp->rx_irq_completion);
 782                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 783                                         0, "McBSP", (void *)mcbsp);
 784                 if (err != 0) {
 785                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 786                                         "for McBSP%d\n", mcbsp->rx_irq,
 787                                         mcbsp->id);
 788                         goto err_free_irq;
 789                 }
 790         }
 791
 792         return 0;
 793 err_free_irq:
 794         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 795 err_clk_disable:
 796         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 797                 mcbsp->pdata->ops->free(id);
 798
 799         /* Do procedure specific to omap34xx arch, if applicable */
 800         omap34xx_mcbsp_free(mcbsp);
 801
 802         clk_disable(mcbsp->fclk);
 803         clk_disable(mcbsp->iclk);
 804
 805         spin_lock(&mcbsp->lock);
 806         mcbsp->free = 1;
 807         mcbsp->reg_cache = NULL;
 808 err_kfree:
 809         spin_unlock(&mcbsp->lock);
 810         kfree(reg_cache);
 811
 812         return err;
 813 }
 814 EXPORT_SYMBOL(omap_mcbsp_request);
 815
 816 void omap_mcbsp_free(unsigned int id)
 817 {
 818         struct omap_mcbsp *mcbsp;
 819         void *reg_cache;
 820
 821         if (!omap_mcbsp_check_valid_id(id)) {
 822                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 823                 return;
 824         }
 825         mcbsp = id_to_mcbsp_ptr(id);
 826
 827         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 828                 mcbsp->pdata->ops->free(id);
 829
 830         /* Do procedure specific to omap34xx arch, if applicable */
 831         omap34xx_mcbsp_free(mcbsp);
 832
 833         clk_disable(mcbsp->fclk);
 834         clk_disable(mcbsp->iclk);
 835
 836         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 837                 /* Free IRQs */
 838                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 839                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 840         }
 841
 842         reg_cache = mcbsp->reg_cache;
 843
 844         spin_lock(&mcbsp->lock);
 845         if (mcbsp->free)
 846                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 847         else
 848                 mcbsp->free = 1;
 849         mcbsp->reg_cache = NULL;
 850         spin_unlock(&mcbsp->lock);
 851
 852         if (reg_cache)
 853                 kfree(reg_cache);
 854 }
 855 EXPORT_SYMBOL(omap_mcbsp_free);
 856
 857 /*
 858  * Here we start the McBSP, by enabling transmitter, receiver or both.
 859  * If no transmitter or receiver is active prior calling, then sample-rate
 860  * generator and frame sync are started.
 861  */
 862 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 863 {
 864         struct omap_mcbsp *mcbsp;
 865         int idle;
 866         u16 w;
 867
 868         if (!omap_mcbsp_check_valid_id(id)) {
 869                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 870                 return;
 871         }
 872         mcbsp = id_to_mcbsp_ptr(id);
 873
 874         if (cpu_is_omap34xx())
 875                 omap_st_start(mcbsp);
 876
 877         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
 878         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 879
 880         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 881                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 882
 883         if (idle) {
 884                 /* Start the sample generator */
 885                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 886                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 887         }
 888
 889         /* Enable transmitter and receiver */
 890         tx &= 1;
 891         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 892         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 893
 894         rx &= 1;
 895         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 896         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 897
 898         /*
 899          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 900          * REVISIT: 100us may give enough time for two CLKSRG, however
 901          * due to some unknown PM related, clock gating etc. reason it
 902          * is now at 500us.
 903          */
 904         udelay(500);
 905
 906         if (idle) {
 907                 /* Start frame sync */
 908                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 909                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 910         }
 911
 912         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 913                 /* Release the transmitter and receiver */
 914                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 915                 w &= ~(tx ? XDISABLE : 0);
 916                 MCBSP_WRITE(mcbsp, XCCR, w);
 917                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 918                 w &= ~(rx ? RDISABLE : 0);
 919                 MCBSP_WRITE(mcbsp, RCCR, w);
 920         }
 921
 922         /* Dump McBSP Regs */
 923         omap_mcbsp_dump_reg(id);
 924 }
 925 EXPORT_SYMBOL(omap_mcbsp_start);
 926
 927 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 928 {
 929         struct omap_mcbsp *mcbsp;
 930         int idle;
 931         u16 w;
 932
 933         if (!omap_mcbsp_check_valid_id(id)) {
 934                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 935                 return;
 936         }
 937
 938         mcbsp = id_to_mcbsp_ptr(id);
 939
 940         /* Reset transmitter */
 941         tx &= 1;
 942         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 943                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 944                 w |= (tx ? XDISABLE : 0);
 945                 MCBSP_WRITE(mcbsp, XCCR, w);
 946         }
 947         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 948         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 949
 950         /* Reset receiver */
 951         rx &= 1;
 952         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 953                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 954                 w |= (rx ? RDISABLE : 0);
 955                 MCBSP_WRITE(mcbsp, RCCR, w);
 956         }
 957         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 958         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 959
 960         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 961                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 962
 963         if (idle) {
 964                 /* Reset the sample rate generator */
 965                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 966                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 967         }
 968
 969         if (cpu_is_omap34xx())
 970                 omap_st_stop(mcbsp);
 971 }
 972 EXPORT_SYMBOL(omap_mcbsp_stop);
 973
 974 /* polled mcbsp i/o operations */
 975 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 976 {
 977         struct omap_mcbsp *mcbsp;
 978
 979         if (!omap_mcbsp_check_valid_id(id)) {
 980                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 981                 return -ENODEV;
 982         }
 983
 984         mcbsp = id_to_mcbsp_ptr(id);
 985
 986         MCBSP_WRITE(mcbsp, DXR1, buf);
 987         /* if frame sync error - clear the error */
 988         if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
 989                 /* clear error */
 990                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
 991                 /* resend */
 992                 return -1;
 993         } else {
 994                 /* wait for transmit confirmation */
 995                 int attemps = 0;
 996                 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
 997                         if (attemps++ > 1000) {
 998                                 MCBSP_WRITE(mcbsp, SPCR2,
 999                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1000                                                 (~XRST));
1001                                 udelay(10);
1002                                 MCBSP_WRITE(mcbsp, SPCR2,
1003                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1004                                                 (XRST));
1005                                 udelay(10);
1006                                 dev_err(mcbsp->dev, "Could not write to"
1007                                         " McBSP%d Register\n", mcbsp->id);
1008                                 return -2;
1009                         }
1010                 }
1011         }
1012
1013         return 0;
1014 }
1015 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1016
1017 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1018 {
1019         struct omap_mcbsp *mcbsp;
1020
1021         if (!omap_mcbsp_check_valid_id(id)) {
1022                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1023                 return -ENODEV;
1024         }
1025         mcbsp = id_to_mcbsp_ptr(id);
1026
1027         /* if frame sync error - clear the error */
1028         if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1029                 /* clear error */
1030                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1031                 /* resend */
1032                 return -1;
1033         } else {
1034                 /* wait for recieve confirmation */
1035                 int attemps = 0;
1036                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1037                         if (attemps++ > 1000) {
1038                                 MCBSP_WRITE(mcbsp, SPCR1,
1039                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1040                                                 (~RRST));
1041                                 udelay(10);
1042                                 MCBSP_WRITE(mcbsp, SPCR1,
1043                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1044                                                 (RRST));
1045                                 udelay(10);
1046                                 dev_err(mcbsp->dev, "Could not read from"
1047                                         " McBSP%d Register\n", mcbsp->id);
1048                                 return -2;
1049                         }
1050                 }
1051         }
1052         *buf = MCBSP_READ(mcbsp, DRR1);
1053
1054         return 0;
1055 }
1056 EXPORT_SYMBOL(omap_mcbsp_pollread);
1057
1058 /*
1059  * IRQ based word transmission.
1060  */
1061 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1062 {
1063         struct omap_mcbsp *mcbsp;
1064         omap_mcbsp_word_length word_length;
1065
1066         if (!omap_mcbsp_check_valid_id(id)) {
1067                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1068                 return;
1069         }
1070
1071         mcbsp = id_to_mcbsp_ptr(id);
1072         word_length = mcbsp->tx_word_length;
1073
1074         wait_for_completion(&mcbsp->tx_irq_completion);
1075
1076         if (word_length > OMAP_MCBSP_WORD_16)
1077                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1078         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1079 }
1080 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1081
1082 u32 omap_mcbsp_recv_word(unsigned int id)
1083 {
1084         struct omap_mcbsp *mcbsp;
1085         u16 word_lsb, word_msb = 0;
1086         omap_mcbsp_word_length word_length;
1087
1088         if (!omap_mcbsp_check_valid_id(id)) {
1089                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1090                 return -ENODEV;
1091         }
1092         mcbsp = id_to_mcbsp_ptr(id);
1093
1094         word_length = mcbsp->rx_word_length;
1095
1096         wait_for_completion(&mcbsp->rx_irq_completion);
1097
1098         if (word_length > OMAP_MCBSP_WORD_16)
1099                 word_msb = MCBSP_READ(mcbsp, DRR2);
1100         word_lsb = MCBSP_READ(mcbsp, DRR1);
1101
1102         return (word_lsb | (word_msb << 16));
1103 }
1104 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1105
1106 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1107 {
1108         struct omap_mcbsp *mcbsp;
1109         omap_mcbsp_word_length tx_word_length;
1110         omap_mcbsp_word_length rx_word_length;
1111         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1112
1113         if (!omap_mcbsp_check_valid_id(id)) {
1114                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1115                 return -ENODEV;
1116         }
1117         mcbsp = id_to_mcbsp_ptr(id);
1118         tx_word_length = mcbsp->tx_word_length;
1119         rx_word_length = mcbsp->rx_word_length;
1120
1121         if (tx_word_length != rx_word_length)
1122                 return -EINVAL;
1123
1124         /* First we wait for the transmitter to be ready */
1125         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1126         while (!(spcr2 & XRDY)) {
1127                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1128                 if (attempts++ > 1000) {
1129                         /* We must reset the transmitter */
1130                         MCBSP_WRITE(mcbsp, SPCR2,
1131                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1132                         udelay(10);
1133                         MCBSP_WRITE(mcbsp, SPCR2,
1134                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1135                         udelay(10);
1136                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1137                                 "ready\n", mcbsp->id);
1138                         return -EAGAIN;
1139                 }
1140         }
1141
1142         /* Now we can push the data */
1143         if (tx_word_length > OMAP_MCBSP_WORD_16)
1144                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1145         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1146
1147         /* We wait for the receiver to be ready */
1148         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1149         while (!(spcr1 & RRDY)) {
1150                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1151                 if (attempts++ > 1000) {
1152                         /* We must reset the receiver */
1153                         MCBSP_WRITE(mcbsp, SPCR1,
1154                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1155                         udelay(10);
1156                         MCBSP_WRITE(mcbsp, SPCR1,
1157                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1158                         udelay(10);
1159                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1160                                 "ready\n", mcbsp->id);
1161                         return -EAGAIN;
1162                 }
1163         }
1164
1165         /* Receiver is ready, let's read the dummy data */
1166         if (rx_word_length > OMAP_MCBSP_WORD_16)
1167                 word_msb = MCBSP_READ(mcbsp, DRR2);
1168         word_lsb = MCBSP_READ(mcbsp, DRR1);
1169
1170         return 0;
1171 }
1172 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1173
1174 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1175 {
1176         struct omap_mcbsp *mcbsp;
1177         u32 clock_word = 0;
1178         omap_mcbsp_word_length tx_word_length;
1179         omap_mcbsp_word_length rx_word_length;
1180         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1181
1182         if (!omap_mcbsp_check_valid_id(id)) {
1183                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1184                 return -ENODEV;
1185         }
1186
1187         mcbsp = id_to_mcbsp_ptr(id);
1188
1189         tx_word_length = mcbsp->tx_word_length;
1190         rx_word_length = mcbsp->rx_word_length;
1191
1192         if (tx_word_length != rx_word_length)
1193                 return -EINVAL;
1194
1195         /* First we wait for the transmitter to be ready */
1196         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1197         while (!(spcr2 & XRDY)) {
1198                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1199                 if (attempts++ > 1000) {
1200                         /* We must reset the transmitter */
1201                         MCBSP_WRITE(mcbsp, SPCR2,
1202                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1203                         udelay(10);
1204                         MCBSP_WRITE(mcbsp, SPCR2,
1205                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1206                         udelay(10);
1207                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1208                                 "ready\n", mcbsp->id);
1209                         return -EAGAIN;
1210                 }
1211         }
1212
1213         /* We first need to enable the bus clock */
1214         if (tx_word_length > OMAP_MCBSP_WORD_16)
1215                 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1216         MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1217
1218         /* We wait for the receiver to be ready */
1219         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1220         while (!(spcr1 & RRDY)) {
1221                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1222                 if (attempts++ > 1000) {
1223                         /* We must reset the receiver */
1224                         MCBSP_WRITE(mcbsp, SPCR1,
1225                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1226                         udelay(10);
1227                         MCBSP_WRITE(mcbsp, SPCR1,
1228                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1229                         udelay(10);
1230                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1231                                 "ready\n", mcbsp->id);
1232                         return -EAGAIN;
1233                 }
1234         }
1235
1236         /* Receiver is ready, there is something for us */
1237         if (rx_word_length > OMAP_MCBSP_WORD_16)
1238                 word_msb = MCBSP_READ(mcbsp, DRR2);
1239         word_lsb = MCBSP_READ(mcbsp, DRR1);
1240
1241         word[0] = (word_lsb | (word_msb << 16));
1242
1243         return 0;
1244 }
1245 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1246
1247 /*
1248  * Simple DMA based buffer rx/tx routines.
1249  * Nothing fancy, just a single buffer tx/rx through DMA.
1250  * The DMA resources are released once the transfer is done.
1251  * For anything fancier, you should use your own customized DMA
1252  * routines and callbacks.
1253  */
1254 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1255                                 unsigned int length)
1256 {
1257         struct omap_mcbsp *mcbsp;
1258         int dma_tx_ch;
1259         int src_port = 0;
1260         int dest_port = 0;
1261         int sync_dev = 0;
1262
1263         if (!omap_mcbsp_check_valid_id(id)) {
1264                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1265                 return -ENODEV;
1266         }
1267         mcbsp = id_to_mcbsp_ptr(id);
1268
1269         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1270                                 omap_mcbsp_tx_dma_callback,
1271                                 mcbsp,
1272                                 &dma_tx_ch)) {
1273                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1274                                 "McBSP%d TX. Trying IRQ based TX\n",
1275                                 mcbsp->id);
1276                 return -EAGAIN;
1277         }
1278         mcbsp->dma_tx_lch = dma_tx_ch;
1279
1280         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1281                 dma_tx_ch);
1282
1283         init_completion(&mcbsp->tx_dma_completion);
1284
1285         if (cpu_class_is_omap1()) {
1286                 src_port = OMAP_DMA_PORT_TIPB;
1287                 dest_port = OMAP_DMA_PORT_EMIFF;
1288         }
1289         if (cpu_class_is_omap2())
1290                 sync_dev = mcbsp->dma_tx_sync;
1291
1292         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1293                                      OMAP_DMA_DATA_TYPE_S16,
1294                                      length >> 1, 1,
1295                                      OMAP_DMA_SYNC_ELEMENT,
1296          sync_dev, 0);
1297
1298         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1299                                  src_port,
1300                                  OMAP_DMA_AMODE_CONSTANT,
1301                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1302                                  0, 0);
1303
1304         omap_set_dma_src_params(mcbsp->dma_tx_lch,
1305                                 dest_port,
1306                                 OMAP_DMA_AMODE_POST_INC,
1307                                 buffer,
1308                                 0, 0);
1309
1310         omap_start_dma(mcbsp->dma_tx_lch);
1311         wait_for_completion(&mcbsp->tx_dma_completion);
1312
1313         return 0;
1314 }
1315 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1316
1317 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1318                                 unsigned int length)
1319 {
1320         struct omap_mcbsp *mcbsp;
1321         int dma_rx_ch;
1322         int src_port = 0;
1323         int dest_port = 0;
1324         int sync_dev = 0;
1325
1326         if (!omap_mcbsp_check_valid_id(id)) {
1327                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1328                 return -ENODEV;
1329         }
1330         mcbsp = id_to_mcbsp_ptr(id);
1331
1332         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1333                                 omap_mcbsp_rx_dma_callback,
1334                                 mcbsp,
1335                                 &dma_rx_ch)) {
1336                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1337                                 "McBSP%d RX. Trying IRQ based RX\n",
1338                                 mcbsp->id);
1339                 return -EAGAIN;
1340         }
1341         mcbsp->dma_rx_lch = dma_rx_ch;
1342
1343         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1344                 dma_rx_ch);
1345
1346         init_completion(&mcbsp->rx_dma_completion);
1347
1348         if (cpu_class_is_omap1()) {
1349                 src_port = OMAP_DMA_PORT_TIPB;
1350                 dest_port = OMAP_DMA_PORT_EMIFF;
1351         }
1352         if (cpu_class_is_omap2())
1353                 sync_dev = mcbsp->dma_rx_sync;
1354
1355         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1356                                         OMAP_DMA_DATA_TYPE_S16,
1357                                         length >> 1, 1,
1358                                         OMAP_DMA_SYNC_ELEMENT,
1359                                         sync_dev, 0);
1360
1361         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1362                                 src_port,
1363                                 OMAP_DMA_AMODE_CONSTANT,
1364                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1365                                 0, 0);
1366
1367         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1368                                         dest_port,
1369                                         OMAP_DMA_AMODE_POST_INC,
1370                                         buffer,
1371                                         0, 0);
1372
1373         omap_start_dma(mcbsp->dma_rx_lch);
1374         wait_for_completion(&mcbsp->rx_dma_completion);
1375
1376         return 0;
1377 }
1378 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1379
1380 /*
1381  * SPI wrapper.
1382  * Since SPI setup is much simpler than the generic McBSP one,
1383  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1384  * Once this is done, you can call omap_mcbsp_start().
1385  */
1386 void omap_mcbsp_set_spi_mode(unsigned int id,
1387                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1388 {
1389         struct omap_mcbsp *mcbsp;
1390         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1391
1392         if (!omap_mcbsp_check_valid_id(id)) {
1393                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1394                 return;
1395         }
1396         mcbsp = id_to_mcbsp_ptr(id);
1397
1398         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1399
1400         /* SPI has only one frame */
1401         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1402         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1403
1404         /* Clock stop mode */
1405         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1406                 mcbsp_cfg.spcr1 |= (1 << 12);
1407         else
1408                 mcbsp_cfg.spcr1 |= (3 << 11);
1409
1410         /* Set clock parities */
1411         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1412                 mcbsp_cfg.pcr0 |= CLKRP;
1413         else
1414                 mcbsp_cfg.pcr0 &= ~CLKRP;
1415
1416         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1417                 mcbsp_cfg.pcr0 &= ~CLKXP;
1418         else
1419                 mcbsp_cfg.pcr0 |= CLKXP;
1420
1421         /* Set SCLKME to 0 and CLKSM to 1 */
1422         mcbsp_cfg.pcr0 &= ~SCLKME;
1423         mcbsp_cfg.srgr2 |= CLKSM;
1424
1425         /* Set FSXP */
1426         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1427                 mcbsp_cfg.pcr0 &= ~FSXP;
1428         else
1429                 mcbsp_cfg.pcr0 |= FSXP;
1430
1431         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1432                 mcbsp_cfg.pcr0 |= CLKXM;
1433                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1434                 mcbsp_cfg.pcr0 |= FSXM;
1435                 mcbsp_cfg.srgr2 &= ~FSGM;
1436                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1437                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1438         } else {
1439                 mcbsp_cfg.pcr0 &= ~CLKXM;
1440                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1441                 mcbsp_cfg.pcr0 &= ~FSXM;
1442                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1443                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1444         }
1445
1446         mcbsp_cfg.xcr2 &= ~XPHASE;
1447         mcbsp_cfg.rcr2 &= ~RPHASE;
1448
1449         omap_mcbsp_config(id, &mcbsp_cfg);
1450 }
1451 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1452
1453 #ifdef CONFIG_ARCH_OMAP3
1454 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1455 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1456 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1457 static ssize_t prop##_show(struct device *dev,                          \
1458                         struct device_attribute *attr, char *buf)       \
1459 {                                                                       \
1460         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1461                                                                         \
1462         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1463 }                                                                       \
1464                                                                         \
1465 static ssize_t prop##_store(struct device *dev,                         \
1466                                 struct device_attribute *attr,          \
1467                                 const char *buf, size_t size)           \
1468 {                                                                       \
1469         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1470         unsigned long val;                                              \
1471         int status;                                                     \
1472                                                                         \
1473         status = strict_strtoul(buf, 0, &val);                          \
1474         if (status)                                                     \
1475                 return status;                                          \
1476                                                                         \
1477         if (!valid_threshold(mcbsp, val))                               \
1478                 return -EDOM;                                           \
1479                                                                         \
1480         mcbsp->prop = val;                                              \
1481         return size;                                                    \
1482 }                                                                       \
1483                                                                         \
1484 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1485
1486 THRESHOLD_PROP_BUILDER(max_tx_thres);
1487 THRESHOLD_PROP_BUILDER(max_rx_thres);
1488
1489 static const char *dma_op_modes[] = {
1490         "element", "threshold", "frame",
1491 };
1492
1493 static ssize_t dma_op_mode_show(struct device *dev,
1494                         struct device_attribute *attr, char *buf)
1495 {
1496         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1497         int dma_op_mode, i = 0;
1498         ssize_t len = 0;
1499         const char * const *s;
1500
1501         dma_op_mode = mcbsp->dma_op_mode;
1502
1503         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1504                 if (dma_op_mode == i)
1505                         len += sprintf(buf + len, "[%s] ", *s);
1506                 else
1507                         len += sprintf(buf + len, "%s ", *s);
1508         }
1509         len += sprintf(buf + len, "\n");
1510
1511         return len;
1512 }
1513
1514 static ssize_t dma_op_mode_store(struct device *dev,
1515                                 struct device_attribute *attr,
1516                                 const char *buf, size_t size)
1517 {
1518         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1519         const char * const *s;
1520         int i = 0;
1521
1522         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1523                 if (sysfs_streq(buf, *s))
1524                         break;
1525
1526         if (i == ARRAY_SIZE(dma_op_modes))
1527                 return -EINVAL;
1528
1529         spin_lock_irq(&mcbsp->lock);
1530         if (!mcbsp->free) {
1531                 size = -EBUSY;
1532                 goto unlock;
1533         }
1534         mcbsp->dma_op_mode = i;
1535
1536 unlock:
1537         spin_unlock_irq(&mcbsp->lock);
1538
1539         return size;
1540 }
1541
1542 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1543
1544 static ssize_t st_taps_show(struct device *dev,
1545                             struct device_attribute *attr, char *buf)
1546 {
1547         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1548         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1549         ssize_t status = 0;
1550         int i;
1551
1552         spin_lock_irq(&mcbsp->lock);
1553         for (i = 0; i < st_data->nr_taps; i++)
1554                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1555                                   st_data->taps[i]);
1556         if (i)
1557                 status += sprintf(&buf[status], "\n");
1558         spin_unlock_irq(&mcbsp->lock);
1559
1560         return status;
1561 }
1562
1563 static ssize_t st_taps_store(struct device *dev,
1564                              struct device_attribute *attr,
1565                              const char *buf, size_t size)
1566 {
1567         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1568         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1569         int val, tmp, status, i = 0;
1570
1571         spin_lock_irq(&mcbsp->lock);
1572         memset(st_data->taps, 0, sizeof(st_data->taps));
1573         st_data->nr_taps = 0;
1574
1575         do {
1576                 status = sscanf(buf, "%d%n", &val, &tmp);
1577                 if (status < 0 || status == 0) {
1578                         size = -EINVAL;
1579                         goto out;
1580                 }
1581                 if (val < -32768 || val > 32767) {
1582                         size = -EINVAL;
1583                         goto out;
1584                 }
1585                 st_data->taps[i++] = val;
1586                 buf += tmp;
1587                 if (*buf != ',')
1588                         break;
1589                 buf++;
1590         } while (1);
1591
1592         st_data->nr_taps = i;
1593
1594 out:
1595         spin_unlock_irq(&mcbsp->lock);
1596
1597         return size;
1598 }
1599
1600 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1601
1602 static const struct attribute *additional_attrs[] = {
1603         &dev_attr_max_tx_thres.attr,
1604         &dev_attr_max_rx_thres.attr,
1605         &dev_attr_dma_op_mode.attr,
1606         NULL,
1607 };
1608
1609 static const struct attribute_group additional_attr_group = {
1610         .attrs = (struct attribute **)additional_attrs,
1611 };
1612
1613 static inline int __devinit omap_additional_add(struct device *dev)
1614 {
1615         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1616 }
1617
1618 static inline void __devexit omap_additional_remove(struct device *dev)
1619 {
1620         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1621 }
1622
1623 static const struct attribute *sidetone_attrs[] = {
1624         &dev_attr_st_taps.attr,
1625         NULL,
1626 };
1627
1628 static const struct attribute_group sidetone_attr_group = {
1629         .attrs = (struct attribute **)sidetone_attrs,
1630 };
1631
1632 int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1633 {
1634         struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1635         struct omap_mcbsp_st_data *st_data;
1636         int err;
1637
1638         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1639         if (!st_data) {
1640                 err = -ENOMEM;
1641                 goto err1;
1642         }
1643
1644         st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1645         if (!st_data->io_base_st) {
1646                 err = -ENOMEM;
1647                 goto err2;
1648         }
1649
1650         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1651         if (err)
1652                 goto err3;
1653
1654         mcbsp->st_data = st_data;
1655         return 0;
1656
1657 err3:
1658         iounmap(st_data->io_base_st);
1659 err2:
1660         kfree(st_data);
1661 err1:
1662         return err;
1663
1664 }
1665
1666 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1667 {
1668         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1669
1670         if (st_data) {
1671                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1672                 iounmap(st_data->io_base_st);
1673                 kfree(st_data);
1674         }
1675 }
1676
1677 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1678 {
1679         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1680         if (cpu_is_omap34xx()) {
1681                 mcbsp->max_tx_thres = max_thres(mcbsp);
1682                 mcbsp->max_rx_thres = max_thres(mcbsp);
1683                 /*
1684                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1685                  * for mcbsp2 instances.
1686                  */
1687                 if (omap_additional_add(mcbsp->dev))
1688                         dev_warn(mcbsp->dev,
1689                                 "Unable to create additional controls\n");
1690
1691                 if (mcbsp->id == 2 || mcbsp->id == 3)
1692                         if (omap_st_add(mcbsp))
1693                                 dev_warn(mcbsp->dev,
1694                                  "Unable to create sidetone controls\n");
1695
1696         } else {
1697                 mcbsp->max_tx_thres = -EINVAL;
1698                 mcbsp->max_rx_thres = -EINVAL;
1699         }
1700 }
1701
1702 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1703 {
1704         if (cpu_is_omap34xx()) {
1705                 omap_additional_remove(mcbsp->dev);
1706
1707                 if (mcbsp->id == 2 || mcbsp->id == 3)
1708                         omap_st_remove(mcbsp);
1709         }
1710 }
1711 #else
1712 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1713 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1714 #endif /* CONFIG_ARCH_OMAP3 */
1715
1716 /*
1717  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1718  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1719  */
1720 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1721 {
1722         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1723         struct omap_mcbsp *mcbsp;
1724         int id = pdev->id - 1;
1725         int ret = 0;
1726
1727         if (!pdata) {
1728                 dev_err(&pdev->dev, "McBSP device initialized without"
1729                                 "platform data\n");
1730                 ret = -EINVAL;
1731                 goto exit;
1732         }
1733
1734         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1735
1736         if (id >= omap_mcbsp_count) {
1737                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1738                 ret = -EINVAL;
1739                 goto exit;
1740         }
1741
1742         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1743         if (!mcbsp) {
1744                 ret = -ENOMEM;
1745                 goto exit;
1746         }
1747
1748         spin_lock_init(&mcbsp->lock);
1749         mcbsp->id = id + 1;
1750         mcbsp->free = 1;
1751         mcbsp->dma_tx_lch = -1;
1752         mcbsp->dma_rx_lch = -1;
1753
1754         mcbsp->phys_base = pdata->phys_base;
1755         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1756         if (!mcbsp->io_base) {
1757                 ret = -ENOMEM;
1758                 goto err_ioremap;
1759         }
1760
1761         /* Default I/O is IRQ based */
1762         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1763         mcbsp->tx_irq = pdata->tx_irq;
1764         mcbsp->rx_irq = pdata->rx_irq;
1765         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1766         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1767
1768         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1769         if (IS_ERR(mcbsp->iclk)) {
1770                 ret = PTR_ERR(mcbsp->iclk);
1771                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1772                 goto err_iclk;
1773         }
1774
1775         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1776         if (IS_ERR(mcbsp->fclk)) {
1777                 ret = PTR_ERR(mcbsp->fclk);
1778                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1779                 goto err_fclk;
1780         }
1781
1782         mcbsp->pdata = pdata;
1783         mcbsp->dev = &pdev->dev;
1784         mcbsp_ptr[id] = mcbsp;
1785         platform_set_drvdata(pdev, mcbsp);
1786
1787         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1788         omap34xx_device_init(mcbsp);
1789
1790         return 0;
1791
1792 err_fclk:
1793         clk_put(mcbsp->iclk);
1794 err_iclk:
1795         iounmap(mcbsp->io_base);
1796 err_ioremap:
1797         kfree(mcbsp);
1798 exit:
1799         return ret;
1800 }
1801
1802 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1803 {
1804         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1805
1806         platform_set_drvdata(pdev, NULL);
1807         if (mcbsp) {
1808
1809                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1810                                 mcbsp->pdata->ops->free)
1811                         mcbsp->pdata->ops->free(mcbsp->id);
1812
1813                 omap34xx_device_exit(mcbsp);
1814
1815                 clk_disable(mcbsp->fclk);
1816                 clk_disable(mcbsp->iclk);
1817                 clk_put(mcbsp->fclk);
1818                 clk_put(mcbsp->iclk);
1819
1820                 iounmap(mcbsp->io_base);
1821
1822                 mcbsp->fclk = NULL;
1823                 mcbsp->iclk = NULL;
1824                 mcbsp->free = 0;
1825                 mcbsp->dev = NULL;
1826         }
1827
1828         return 0;
1829 }
1830
1831 static struct platform_driver omap_mcbsp_driver = {
1832         .probe          = omap_mcbsp_probe,
1833         .remove         = __devexit_p(omap_mcbsp_remove),
1834         .driver         = {
1835                 .name   = "omap-mcbsp",
1836         },
1837 };
1838
1839 int __init omap_mcbsp_init(void)
1840 {
1841         /* Register the McBSP driver */
1842         return platform_driver_register(&omap_mcbsp_driver);
1843 }