2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
21 #include <asm/hardware.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
30 * OMAP1510 GPIO registers
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
41 #define OMAP1510_IH_GPIO_BASE 64
44 * OMAP1610 specific GPIO registers
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69 * OMAP730 specific GPIO registers
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
85 * omap24xx specific GPIO registers
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
137 u16 virtual_irq_start;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
156 #define METHOD_MPUIO 0
157 #define METHOD_GPIO_1510 1
158 #define METHOD_GPIO_1610 2
159 #define METHOD_GPIO_730 3
160 #define METHOD_GPIO_24XX 4
162 #ifdef CONFIG_ARCH_OMAP16XX
163 static struct gpio_bank gpio_bank_1610[5] = {
164 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
165 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
172 #ifdef CONFIG_ARCH_OMAP15XX
173 static struct gpio_bank gpio_bank_1510[2] = {
174 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
175 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
179 #ifdef CONFIG_ARCH_OMAP730
180 static struct gpio_bank gpio_bank_730[7] = {
181 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
182 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
183 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
184 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
185 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
186 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
187 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
191 #ifdef CONFIG_ARCH_OMAP24XX
193 static struct gpio_bank gpio_bank_242x[4] = {
194 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
200 static struct gpio_bank gpio_bank_243x[5] = {
201 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
210 #ifdef CONFIG_ARCH_OMAP34XX
211 static struct gpio_bank gpio_bank_34xx[6] = {
212 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
222 static struct gpio_bank *gpio_bank;
223 static int gpio_bank_count;
225 static inline struct gpio_bank *get_gpio_bank(int gpio)
227 if (cpu_is_omap15xx()) {
228 if (OMAP_GPIO_IS_MPUIO(gpio))
229 return &gpio_bank[0];
230 return &gpio_bank[1];
232 if (cpu_is_omap16xx()) {
233 if (OMAP_GPIO_IS_MPUIO(gpio))
234 return &gpio_bank[0];
235 return &gpio_bank[1 + (gpio >> 4)];
237 if (cpu_is_omap730()) {
238 if (OMAP_GPIO_IS_MPUIO(gpio))
239 return &gpio_bank[0];
240 return &gpio_bank[1 + (gpio >> 5)];
242 if (cpu_is_omap24xx())
243 return &gpio_bank[gpio >> 5];
244 if (cpu_is_omap34xx())
245 return &gpio_bank[gpio >> 5];
248 static inline int get_gpio_index(int gpio)
250 if (cpu_is_omap730())
252 if (cpu_is_omap24xx())
254 if (cpu_is_omap34xx())
259 static inline int gpio_valid(int gpio)
263 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
264 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
268 if (cpu_is_omap15xx() && gpio < 16)
270 if ((cpu_is_omap16xx()) && gpio < 64)
272 if (cpu_is_omap730() && gpio < 192)
274 if (cpu_is_omap24xx() && gpio < 128)
276 if (cpu_is_omap34xx() && gpio < 160)
281 static int check_gpio(int gpio)
283 if (unlikely(gpio_valid(gpio)) < 0) {
284 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
291 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
293 void __iomem *reg = bank->base;
296 switch (bank->method) {
297 #ifdef CONFIG_ARCH_OMAP1
299 reg += OMAP_MPUIO_IO_CNTL;
302 #ifdef CONFIG_ARCH_OMAP15XX
303 case METHOD_GPIO_1510:
304 reg += OMAP1510_GPIO_DIR_CONTROL;
307 #ifdef CONFIG_ARCH_OMAP16XX
308 case METHOD_GPIO_1610:
309 reg += OMAP1610_GPIO_DIRECTION;
312 #ifdef CONFIG_ARCH_OMAP730
313 case METHOD_GPIO_730:
314 reg += OMAP730_GPIO_DIR_CONTROL;
317 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
318 case METHOD_GPIO_24XX:
319 reg += OMAP24XX_GPIO_OE;
326 l = __raw_readl(reg);
331 __raw_writel(l, reg);
334 void omap_set_gpio_direction(int gpio, int is_input)
336 struct gpio_bank *bank;
338 if (check_gpio(gpio) < 0)
340 bank = get_gpio_bank(gpio);
341 spin_lock(&bank->lock);
342 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
343 spin_unlock(&bank->lock);
346 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
348 void __iomem *reg = bank->base;
351 switch (bank->method) {
352 #ifdef CONFIG_ARCH_OMAP1
354 reg += OMAP_MPUIO_OUTPUT;
355 l = __raw_readl(reg);
362 #ifdef CONFIG_ARCH_OMAP15XX
363 case METHOD_GPIO_1510:
364 reg += OMAP1510_GPIO_DATA_OUTPUT;
365 l = __raw_readl(reg);
372 #ifdef CONFIG_ARCH_OMAP16XX
373 case METHOD_GPIO_1610:
375 reg += OMAP1610_GPIO_SET_DATAOUT;
377 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
381 #ifdef CONFIG_ARCH_OMAP730
382 case METHOD_GPIO_730:
383 reg += OMAP730_GPIO_DATA_OUTPUT;
384 l = __raw_readl(reg);
391 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
392 case METHOD_GPIO_24XX:
394 reg += OMAP24XX_GPIO_SETDATAOUT;
396 reg += OMAP24XX_GPIO_CLEARDATAOUT;
404 __raw_writel(l, reg);
407 void omap_set_gpio_dataout(int gpio, int enable)
409 struct gpio_bank *bank;
411 if (check_gpio(gpio) < 0)
413 bank = get_gpio_bank(gpio);
414 spin_lock(&bank->lock);
415 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
416 spin_unlock(&bank->lock);
419 int omap_get_gpio_datain(int gpio)
421 struct gpio_bank *bank;
424 if (check_gpio(gpio) < 0)
426 bank = get_gpio_bank(gpio);
428 switch (bank->method) {
429 #ifdef CONFIG_ARCH_OMAP1
431 reg += OMAP_MPUIO_INPUT_LATCH;
434 #ifdef CONFIG_ARCH_OMAP15XX
435 case METHOD_GPIO_1510:
436 reg += OMAP1510_GPIO_DATA_INPUT;
439 #ifdef CONFIG_ARCH_OMAP16XX
440 case METHOD_GPIO_1610:
441 reg += OMAP1610_GPIO_DATAIN;
444 #ifdef CONFIG_ARCH_OMAP730
445 case METHOD_GPIO_730:
446 reg += OMAP730_GPIO_DATA_INPUT;
449 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
450 case METHOD_GPIO_24XX:
451 reg += OMAP24XX_GPIO_DATAIN;
457 return (__raw_readl(reg)
458 & (1 << get_gpio_index(gpio))) != 0;
461 #define MOD_REG_BIT(reg, bit_mask, set) \
463 int l = __raw_readl(base + reg); \
464 if (set) l |= bit_mask; \
465 else l &= ~bit_mask; \
466 __raw_writel(l, base + reg); \
469 void omap_set_gpio_debounce(int gpio, int enable)
471 struct gpio_bank *bank;
473 u32 val, l = 1 << get_gpio_index(gpio);
475 if (cpu_class_is_omap1())
478 bank = get_gpio_bank(gpio);
481 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
482 val = __raw_readl(reg);
489 __raw_writel(val, reg);
491 EXPORT_SYMBOL(omap_set_gpio_debounce);
493 void omap_set_gpio_debounce_time(int gpio, int enc_time)
495 struct gpio_bank *bank;
498 if (cpu_class_is_omap1())
501 bank = get_gpio_bank(gpio);
505 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
506 __raw_writel(enc_time, reg);
508 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
510 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
511 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
514 void __iomem *base = bank->base;
515 u32 gpio_bit = 1 << gpio;
517 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
518 trigger & __IRQT_LOWLVL);
519 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
520 trigger & __IRQT_HIGHLVL);
521 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
522 trigger & __IRQT_RISEDGE);
523 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
524 trigger & __IRQT_FALEDGE);
526 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
528 __raw_writel(1 << gpio, bank->base
529 + OMAP24XX_GPIO_SETWKUENA);
531 __raw_writel(1 << gpio, bank->base
532 + OMAP24XX_GPIO_CLEARWKUENA);
535 bank->enabled_non_wakeup_gpios |= gpio_bit;
537 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
541 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
542 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
546 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
548 void __iomem *reg = bank->base;
551 switch (bank->method) {
552 #ifdef CONFIG_ARCH_OMAP1
554 reg += OMAP_MPUIO_GPIO_INT_EDGE;
555 l = __raw_readl(reg);
556 if (trigger & __IRQT_RISEDGE)
558 else if (trigger & __IRQT_FALEDGE)
564 #ifdef CONFIG_ARCH_OMAP15XX
565 case METHOD_GPIO_1510:
566 reg += OMAP1510_GPIO_INT_CONTROL;
567 l = __raw_readl(reg);
568 if (trigger & __IRQT_RISEDGE)
570 else if (trigger & __IRQT_FALEDGE)
576 #ifdef CONFIG_ARCH_OMAP16XX
577 case METHOD_GPIO_1610:
579 reg += OMAP1610_GPIO_EDGE_CTRL2;
581 reg += OMAP1610_GPIO_EDGE_CTRL1;
583 l = __raw_readl(reg);
584 l &= ~(3 << (gpio << 1));
585 if (trigger & __IRQT_RISEDGE)
586 l |= 2 << (gpio << 1);
587 if (trigger & __IRQT_FALEDGE)
588 l |= 1 << (gpio << 1);
590 /* Enable wake-up during idle for dynamic tick */
591 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
596 #ifdef CONFIG_ARCH_OMAP730
597 case METHOD_GPIO_730:
598 reg += OMAP730_GPIO_INT_CONTROL;
599 l = __raw_readl(reg);
600 if (trigger & __IRQT_RISEDGE)
602 else if (trigger & __IRQT_FALEDGE)
608 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
609 case METHOD_GPIO_24XX:
610 set_24xx_gpio_triggering(bank, gpio, trigger);
616 __raw_writel(l, reg);
622 static int gpio_irq_type(unsigned irq, unsigned type)
624 struct gpio_bank *bank;
628 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
629 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
631 gpio = irq - IH_GPIO_BASE;
633 if (check_gpio(gpio) < 0)
636 if (type & ~IRQ_TYPE_SENSE_MASK)
639 /* OMAP1 allows only only edge triggering */
640 if (!cpu_class_is_omap2()
641 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
644 bank = get_irq_chip_data(irq);
645 spin_lock(&bank->lock);
646 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
648 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
649 irq_desc[irq].status |= type;
651 spin_unlock(&bank->lock);
653 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
654 __set_irq_handler_unlocked(irq, handle_level_irq);
655 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
656 __set_irq_handler_unlocked(irq, handle_edge_irq);
661 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
663 void __iomem *reg = bank->base;
665 switch (bank->method) {
666 #ifdef CONFIG_ARCH_OMAP1
668 /* MPUIO irqstatus is reset by reading the status register,
669 * so do nothing here */
672 #ifdef CONFIG_ARCH_OMAP15XX
673 case METHOD_GPIO_1510:
674 reg += OMAP1510_GPIO_INT_STATUS;
677 #ifdef CONFIG_ARCH_OMAP16XX
678 case METHOD_GPIO_1610:
679 reg += OMAP1610_GPIO_IRQSTATUS1;
682 #ifdef CONFIG_ARCH_OMAP730
683 case METHOD_GPIO_730:
684 reg += OMAP730_GPIO_INT_STATUS;
687 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
688 case METHOD_GPIO_24XX:
689 reg += OMAP24XX_GPIO_IRQSTATUS1;
696 __raw_writel(gpio_mask, reg);
698 /* Workaround for clearing DSP GPIO interrupts to allow retention */
699 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
700 if (cpu_is_omap24xx() || cpu_is_omap34xx())
701 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
705 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
707 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
710 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
712 void __iomem *reg = bank->base;
717 switch (bank->method) {
718 #ifdef CONFIG_ARCH_OMAP1
720 reg += OMAP_MPUIO_GPIO_MASKIT;
725 #ifdef CONFIG_ARCH_OMAP15XX
726 case METHOD_GPIO_1510:
727 reg += OMAP1510_GPIO_INT_MASK;
732 #ifdef CONFIG_ARCH_OMAP16XX
733 case METHOD_GPIO_1610:
734 reg += OMAP1610_GPIO_IRQENABLE1;
738 #ifdef CONFIG_ARCH_OMAP730
739 case METHOD_GPIO_730:
740 reg += OMAP730_GPIO_INT_MASK;
745 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
746 case METHOD_GPIO_24XX:
747 reg += OMAP24XX_GPIO_IRQENABLE1;
756 l = __raw_readl(reg);
763 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
765 void __iomem *reg = bank->base;
768 switch (bank->method) {
769 #ifdef CONFIG_ARCH_OMAP1
771 reg += OMAP_MPUIO_GPIO_MASKIT;
772 l = __raw_readl(reg);
779 #ifdef CONFIG_ARCH_OMAP15XX
780 case METHOD_GPIO_1510:
781 reg += OMAP1510_GPIO_INT_MASK;
782 l = __raw_readl(reg);
789 #ifdef CONFIG_ARCH_OMAP16XX
790 case METHOD_GPIO_1610:
792 reg += OMAP1610_GPIO_SET_IRQENABLE1;
794 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
798 #ifdef CONFIG_ARCH_OMAP730
799 case METHOD_GPIO_730:
800 reg += OMAP730_GPIO_INT_MASK;
801 l = __raw_readl(reg);
808 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
809 case METHOD_GPIO_24XX:
811 reg += OMAP24XX_GPIO_SETIRQENABLE1;
813 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
821 __raw_writel(l, reg);
824 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
826 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
830 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
831 * 1510 does not seem to have a wake-up register. If JTAG is connected
832 * to the target, system will wake up always on GPIO events. While
833 * system is running all registered GPIO interrupts need to have wake-up
834 * enabled. When system is suspended, only selected GPIO interrupts need
835 * to have wake-up enabled.
837 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
839 switch (bank->method) {
840 #ifdef CONFIG_ARCH_OMAP16XX
842 case METHOD_GPIO_1610:
843 spin_lock(&bank->lock);
845 bank->suspend_wakeup |= (1 << gpio);
846 enable_irq_wake(bank->irq);
848 disable_irq_wake(bank->irq);
849 bank->suspend_wakeup &= ~(1 << gpio);
851 spin_unlock(&bank->lock);
854 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
855 case METHOD_GPIO_24XX:
856 if (bank->non_wakeup_gpios & (1 << gpio)) {
857 printk(KERN_ERR "Unable to modify wakeup on "
858 "non-wakeup GPIO%d\n",
859 (bank - gpio_bank) * 32 + gpio);
862 spin_lock(&bank->lock);
864 bank->suspend_wakeup |= (1 << gpio);
865 enable_irq_wake(bank->irq);
867 disable_irq_wake(bank->irq);
868 bank->suspend_wakeup &= ~(1 << gpio);
870 spin_unlock(&bank->lock);
874 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
880 static void _reset_gpio(struct gpio_bank *bank, int gpio)
882 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
883 _set_gpio_irqenable(bank, gpio, 0);
884 _clear_gpio_irqstatus(bank, gpio);
885 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
888 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
889 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
891 unsigned int gpio = irq - IH_GPIO_BASE;
892 struct gpio_bank *bank;
895 if (check_gpio(gpio) < 0)
897 bank = get_irq_chip_data(irq);
898 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
903 int omap_request_gpio(int gpio)
905 struct gpio_bank *bank;
907 if (check_gpio(gpio) < 0)
910 bank = get_gpio_bank(gpio);
911 spin_lock(&bank->lock);
912 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
913 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
915 spin_unlock(&bank->lock);
918 bank->reserved_map |= (1 << get_gpio_index(gpio));
920 /* Set trigger to none. You need to enable the desired trigger with
921 * request_irq() or set_irq_type().
923 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
925 #ifdef CONFIG_ARCH_OMAP15XX
926 if (bank->method == METHOD_GPIO_1510) {
929 /* Claim the pin for MPU */
930 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
931 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
934 spin_unlock(&bank->lock);
939 void omap_free_gpio(int gpio)
941 struct gpio_bank *bank;
943 if (check_gpio(gpio) < 0)
945 bank = get_gpio_bank(gpio);
946 spin_lock(&bank->lock);
947 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
948 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
950 spin_unlock(&bank->lock);
953 #ifdef CONFIG_ARCH_OMAP16XX
954 if (bank->method == METHOD_GPIO_1610) {
955 /* Disable wake-up during idle for dynamic tick */
956 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
957 __raw_writel(1 << get_gpio_index(gpio), reg);
960 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
961 if (bank->method == METHOD_GPIO_24XX) {
962 /* Disable wake-up during idle for dynamic tick */
963 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
964 __raw_writel(1 << get_gpio_index(gpio), reg);
967 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
968 _reset_gpio(bank, gpio);
969 spin_unlock(&bank->lock);
973 * We need to unmask the GPIO bank interrupt as soon as possible to
974 * avoid missing GPIO interrupts for other lines in the bank.
975 * Then we need to mask-read-clear-unmask the triggered GPIO lines
976 * in the bank to avoid missing nested interrupts for a GPIO line.
977 * If we wait to unmask individual GPIO lines in the bank after the
978 * line's interrupt handler has been run, we may miss some nested
981 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
983 void __iomem *isr_reg = NULL;
985 unsigned int gpio_irq;
986 struct gpio_bank *bank;
990 desc->chip->ack(irq);
992 bank = get_irq_data(irq);
993 #ifdef CONFIG_ARCH_OMAP1
994 if (bank->method == METHOD_MPUIO)
995 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
997 #ifdef CONFIG_ARCH_OMAP15XX
998 if (bank->method == METHOD_GPIO_1510)
999 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1001 #if defined(CONFIG_ARCH_OMAP16XX)
1002 if (bank->method == METHOD_GPIO_1610)
1003 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1005 #ifdef CONFIG_ARCH_OMAP730
1006 if (bank->method == METHOD_GPIO_730)
1007 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1009 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1010 if (bank->method == METHOD_GPIO_24XX)
1011 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1014 u32 isr_saved, level_mask = 0;
1017 enabled = _get_gpio_irqbank_mask(bank);
1018 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1020 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1023 if (cpu_class_is_omap2()) {
1024 level_mask = bank->level_mask & enabled;
1027 /* clear edge sensitive interrupts before handler(s) are
1028 called so that we don't miss any interrupt occurred while
1030 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1031 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1032 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1034 /* if there is only edge sensitive GPIO pin interrupts
1035 configured, we could unmask GPIO bank interrupt immediately */
1036 if (!level_mask && !unmasked) {
1038 desc->chip->unmask(irq);
1046 gpio_irq = bank->virtual_irq_start;
1047 for (; isr != 0; isr >>= 1, gpio_irq++) {
1052 d = irq_desc + gpio_irq;
1054 desc_handle_irq(gpio_irq, d);
1057 /* if bank has any level sensitive GPIO pin interrupt
1058 configured, we must unmask the bank interrupt only after
1059 handler(s) are executed in order to avoid spurious bank
1062 desc->chip->unmask(irq);
1066 static void gpio_irq_shutdown(unsigned int irq)
1068 unsigned int gpio = irq - IH_GPIO_BASE;
1069 struct gpio_bank *bank = get_irq_chip_data(irq);
1071 _reset_gpio(bank, gpio);
1074 static void gpio_ack_irq(unsigned int irq)
1076 unsigned int gpio = irq - IH_GPIO_BASE;
1077 struct gpio_bank *bank = get_irq_chip_data(irq);
1079 _clear_gpio_irqstatus(bank, gpio);
1082 static void gpio_mask_irq(unsigned int irq)
1084 unsigned int gpio = irq - IH_GPIO_BASE;
1085 struct gpio_bank *bank = get_irq_chip_data(irq);
1087 _set_gpio_irqenable(bank, gpio, 0);
1090 static void gpio_unmask_irq(unsigned int irq)
1092 unsigned int gpio = irq - IH_GPIO_BASE;
1093 struct gpio_bank *bank = get_irq_chip_data(irq);
1094 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1096 /* For level-triggered GPIOs, the clearing must be done after
1097 * the HW source is cleared, thus after the handler has run */
1098 if (bank->level_mask & irq_mask) {
1099 _set_gpio_irqenable(bank, gpio, 0);
1100 _clear_gpio_irqstatus(bank, gpio);
1103 _set_gpio_irqenable(bank, gpio, 1);
1106 static struct irq_chip gpio_irq_chip = {
1108 .shutdown = gpio_irq_shutdown,
1109 .ack = gpio_ack_irq,
1110 .mask = gpio_mask_irq,
1111 .unmask = gpio_unmask_irq,
1112 .set_type = gpio_irq_type,
1113 .set_wake = gpio_wake_enable,
1116 /*---------------------------------------------------------------------*/
1118 #ifdef CONFIG_ARCH_OMAP1
1120 /* MPUIO uses the always-on 32k clock */
1122 static void mpuio_ack_irq(unsigned int irq)
1124 /* The ISR is reset automatically, so do nothing here. */
1127 static void mpuio_mask_irq(unsigned int irq)
1129 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1130 struct gpio_bank *bank = get_irq_chip_data(irq);
1132 _set_gpio_irqenable(bank, gpio, 0);
1135 static void mpuio_unmask_irq(unsigned int irq)
1137 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1138 struct gpio_bank *bank = get_irq_chip_data(irq);
1140 _set_gpio_irqenable(bank, gpio, 1);
1143 static struct irq_chip mpuio_irq_chip = {
1145 .ack = mpuio_ack_irq,
1146 .mask = mpuio_mask_irq,
1147 .unmask = mpuio_unmask_irq,
1148 .set_type = gpio_irq_type,
1149 #ifdef CONFIG_ARCH_OMAP16XX
1150 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1151 .set_wake = gpio_wake_enable,
1156 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1159 #ifdef CONFIG_ARCH_OMAP16XX
1161 #include <linux/platform_device.h>
1163 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1165 struct gpio_bank *bank = platform_get_drvdata(pdev);
1166 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1168 spin_lock(&bank->lock);
1169 bank->saved_wakeup = __raw_readl(mask_reg);
1170 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1171 spin_unlock(&bank->lock);
1176 static int omap_mpuio_resume_early(struct platform_device *pdev)
1178 struct gpio_bank *bank = platform_get_drvdata(pdev);
1179 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1181 spin_lock(&bank->lock);
1182 __raw_writel(bank->saved_wakeup, mask_reg);
1183 spin_unlock(&bank->lock);
1188 /* use platform_driver for this, now that there's no longer any
1189 * point to sys_device (other than not disturbing old code).
1191 static struct platform_driver omap_mpuio_driver = {
1192 .suspend_late = omap_mpuio_suspend_late,
1193 .resume_early = omap_mpuio_resume_early,
1199 static struct platform_device omap_mpuio_device = {
1203 .driver = &omap_mpuio_driver.driver,
1205 /* could list the /proc/iomem resources */
1208 static inline void mpuio_init(void)
1210 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1212 if (platform_driver_register(&omap_mpuio_driver) == 0)
1213 (void) platform_device_register(&omap_mpuio_device);
1217 static inline void mpuio_init(void) {}
1222 extern struct irq_chip mpuio_irq_chip;
1224 #define bank_is_mpuio(bank) 0
1225 static inline void mpuio_init(void) {}
1229 /*---------------------------------------------------------------------*/
1231 static int initialized;
1232 #if !defined(CONFIG_ARCH_OMAP3)
1233 static struct clk * gpio_ick;
1236 #if defined(CONFIG_ARCH_OMAP2)
1237 static struct clk * gpio_fck;
1240 #if defined(CONFIG_ARCH_OMAP2430)
1241 static struct clk * gpio5_ick;
1242 static struct clk * gpio5_fck;
1245 #if defined(CONFIG_ARCH_OMAP3)
1246 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1247 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1250 static int __init _omap_gpio_init(void)
1253 struct gpio_bank *bank;
1254 #if defined(CONFIG_ARCH_OMAP3)
1260 #if defined(CONFIG_ARCH_OMAP1)
1261 if (cpu_is_omap15xx()) {
1262 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1263 if (IS_ERR(gpio_ick))
1264 printk("Could not get arm_gpio_ck\n");
1266 clk_enable(gpio_ick);
1269 #if defined(CONFIG_ARCH_OMAP2)
1270 if (cpu_class_is_omap2()) {
1271 gpio_ick = clk_get(NULL, "gpios_ick");
1272 if (IS_ERR(gpio_ick))
1273 printk("Could not get gpios_ick\n");
1275 clk_enable(gpio_ick);
1276 gpio_fck = clk_get(NULL, "gpios_fck");
1277 if (IS_ERR(gpio_fck))
1278 printk("Could not get gpios_fck\n");
1280 clk_enable(gpio_fck);
1283 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1285 #if defined(CONFIG_ARCH_OMAP2430)
1286 if (cpu_is_omap2430()) {
1287 gpio5_ick = clk_get(NULL, "gpio5_ick");
1288 if (IS_ERR(gpio5_ick))
1289 printk("Could not get gpio5_ick\n");
1291 clk_enable(gpio5_ick);
1292 gpio5_fck = clk_get(NULL, "gpio5_fck");
1293 if (IS_ERR(gpio5_fck))
1294 printk("Could not get gpio5_fck\n");
1296 clk_enable(gpio5_fck);
1302 #if defined(CONFIG_ARCH_OMAP3)
1303 if (cpu_is_omap34xx()) {
1304 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1305 sprintf(clk_name, "gpio%d_ick", i + 1);
1306 gpio_iclks[i] = clk_get(NULL, clk_name);
1307 if (IS_ERR(gpio_iclks[i]))
1308 printk(KERN_ERR "Could not get %s\n", clk_name);
1310 clk_enable(gpio_iclks[i]);
1311 sprintf(clk_name, "gpio%d_fck", i + 1);
1312 gpio_fclks[i] = clk_get(NULL, clk_name);
1313 if (IS_ERR(gpio_fclks[i]))
1314 printk(KERN_ERR "Could not get %s\n", clk_name);
1316 clk_enable(gpio_fclks[i]);
1322 #ifdef CONFIG_ARCH_OMAP15XX
1323 if (cpu_is_omap15xx()) {
1324 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1325 gpio_bank_count = 2;
1326 gpio_bank = gpio_bank_1510;
1329 #if defined(CONFIG_ARCH_OMAP16XX)
1330 if (cpu_is_omap16xx()) {
1333 gpio_bank_count = 5;
1334 gpio_bank = gpio_bank_1610;
1335 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1336 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1337 (rev >> 4) & 0x0f, rev & 0x0f);
1340 #ifdef CONFIG_ARCH_OMAP730
1341 if (cpu_is_omap730()) {
1342 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1343 gpio_bank_count = 7;
1344 gpio_bank = gpio_bank_730;
1348 #ifdef CONFIG_ARCH_OMAP24XX
1349 if (cpu_is_omap242x()) {
1352 gpio_bank_count = 4;
1353 gpio_bank = gpio_bank_242x;
1354 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1355 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1356 (rev >> 4) & 0x0f, rev & 0x0f);
1358 if (cpu_is_omap243x()) {
1361 gpio_bank_count = 5;
1362 gpio_bank = gpio_bank_243x;
1363 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1364 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1365 (rev >> 4) & 0x0f, rev & 0x0f);
1368 #ifdef CONFIG_ARCH_OMAP34XX
1369 if (cpu_is_omap34xx()) {
1372 gpio_bank_count = OMAP34XX_NR_GPIOS;
1373 gpio_bank = gpio_bank_34xx;
1374 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1375 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1376 (rev >> 4) & 0x0f, rev & 0x0f);
1379 for (i = 0; i < gpio_bank_count; i++) {
1380 int j, gpio_count = 16;
1382 bank = &gpio_bank[i];
1383 bank->reserved_map = 0;
1384 bank->base = IO_ADDRESS(bank->base);
1385 spin_lock_init(&bank->lock);
1386 if (bank_is_mpuio(bank))
1387 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1388 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1389 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1390 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1392 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1393 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1394 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1395 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1397 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1398 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1399 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1401 gpio_count = 32; /* 730 has 32-bit GPIOs */
1404 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1405 if (bank->method == METHOD_GPIO_24XX) {
1406 static const u32 non_wakeup_gpios[] = {
1407 0xe203ffc0, 0x08700040
1410 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1411 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1412 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1414 /* Initialize interface clock ungated, module enabled */
1415 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1416 if (i < ARRAY_SIZE(non_wakeup_gpios))
1417 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1421 for (j = bank->virtual_irq_start;
1422 j < bank->virtual_irq_start + gpio_count; j++) {
1423 set_irq_chip_data(j, bank);
1424 if (bank_is_mpuio(bank))
1425 set_irq_chip(j, &mpuio_irq_chip);
1427 set_irq_chip(j, &gpio_irq_chip);
1428 set_irq_handler(j, handle_simple_irq);
1429 set_irq_flags(j, IRQF_VALID);
1431 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1432 set_irq_data(bank->irq, bank);
1435 /* Enable system clock for GPIO module.
1436 * The CAM_CLK_CTRL *is* really the right place. */
1437 if (cpu_is_omap16xx())
1438 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1440 /* Enable autoidle for the OCP interface */
1441 if (cpu_is_omap24xx())
1442 omap_writel(1 << 0, 0x48019010);
1443 if (cpu_is_omap34xx())
1444 omap_writel(1 << 0, 0x48306814);
1449 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1450 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1454 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1457 for (i = 0; i < gpio_bank_count; i++) {
1458 struct gpio_bank *bank = &gpio_bank[i];
1459 void __iomem *wake_status;
1460 void __iomem *wake_clear;
1461 void __iomem *wake_set;
1463 switch (bank->method) {
1464 #ifdef CONFIG_ARCH_OMAP16XX
1465 case METHOD_GPIO_1610:
1466 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1467 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1468 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1471 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1472 case METHOD_GPIO_24XX:
1473 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1474 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1475 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1482 spin_lock(&bank->lock);
1483 bank->saved_wakeup = __raw_readl(wake_status);
1484 __raw_writel(0xffffffff, wake_clear);
1485 __raw_writel(bank->suspend_wakeup, wake_set);
1486 spin_unlock(&bank->lock);
1492 static int omap_gpio_resume(struct sys_device *dev)
1496 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1499 for (i = 0; i < gpio_bank_count; i++) {
1500 struct gpio_bank *bank = &gpio_bank[i];
1501 void __iomem *wake_clear;
1502 void __iomem *wake_set;
1504 switch (bank->method) {
1505 #ifdef CONFIG_ARCH_OMAP16XX
1506 case METHOD_GPIO_1610:
1507 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1508 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1511 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1512 case METHOD_GPIO_24XX:
1513 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1514 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1521 spin_lock(&bank->lock);
1522 __raw_writel(0xffffffff, wake_clear);
1523 __raw_writel(bank->saved_wakeup, wake_set);
1524 spin_unlock(&bank->lock);
1530 static struct sysdev_class omap_gpio_sysclass = {
1532 .suspend = omap_gpio_suspend,
1533 .resume = omap_gpio_resume,
1536 static struct sys_device omap_gpio_device = {
1538 .cls = &omap_gpio_sysclass,
1543 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1545 static int workaround_enabled;
1547 void omap2_gpio_prepare_for_retention(void)
1551 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1552 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1553 for (i = 0; i < gpio_bank_count; i++) {
1554 struct gpio_bank *bank = &gpio_bank[i];
1557 if (!(bank->enabled_non_wakeup_gpios))
1559 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1560 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1561 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1562 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1564 bank->saved_fallingdetect = l1;
1565 bank->saved_risingdetect = l2;
1566 l1 &= ~bank->enabled_non_wakeup_gpios;
1567 l2 &= ~bank->enabled_non_wakeup_gpios;
1568 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1569 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1570 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1575 workaround_enabled = 0;
1578 workaround_enabled = 1;
1581 void omap2_gpio_resume_after_retention(void)
1585 if (!workaround_enabled)
1587 for (i = 0; i < gpio_bank_count; i++) {
1588 struct gpio_bank *bank = &gpio_bank[i];
1591 if (!(bank->enabled_non_wakeup_gpios))
1593 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1594 __raw_writel(bank->saved_fallingdetect,
1595 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1596 __raw_writel(bank->saved_risingdetect,
1597 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1599 /* Check if any of the non-wakeup interrupt GPIOs have changed
1600 * state. If so, generate an IRQ by software. This is
1601 * horribly racy, but it's the best we can do to work around
1602 * this silicon bug. */
1603 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1604 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1606 l ^= bank->saved_datain;
1607 l &= bank->non_wakeup_gpios;
1610 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1611 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1612 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1613 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1614 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1615 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1616 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1626 * This may get called early from board specific init
1627 * for boards that have interrupts routed via FPGA.
1629 int __init omap_gpio_init(void)
1632 return _omap_gpio_init();
1637 static int __init omap_gpio_sysinit(void)
1642 ret = _omap_gpio_init();
1646 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1647 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1649 ret = sysdev_class_register(&omap_gpio_sysclass);
1651 ret = sysdev_register(&omap_gpio_device);
1659 EXPORT_SYMBOL(omap_request_gpio);
1660 EXPORT_SYMBOL(omap_free_gpio);
1661 EXPORT_SYMBOL(omap_set_gpio_direction);
1662 EXPORT_SYMBOL(omap_set_gpio_dataout);
1663 EXPORT_SYMBOL(omap_get_gpio_datain);
1665 arch_initcall(omap_gpio_sysinit);
1668 #ifdef CONFIG_DEBUG_FS
1670 #include <linux/debugfs.h>
1671 #include <linux/seq_file.h>
1673 static int gpio_is_input(struct gpio_bank *bank, int mask)
1675 void __iomem *reg = bank->base;
1677 switch (bank->method) {
1679 reg += OMAP_MPUIO_IO_CNTL;
1681 case METHOD_GPIO_1510:
1682 reg += OMAP1510_GPIO_DIR_CONTROL;
1684 case METHOD_GPIO_1610:
1685 reg += OMAP1610_GPIO_DIRECTION;
1687 case METHOD_GPIO_730:
1688 reg += OMAP730_GPIO_DIR_CONTROL;
1690 case METHOD_GPIO_24XX:
1691 reg += OMAP24XX_GPIO_OE;
1694 return __raw_readl(reg) & mask;
1698 static int dbg_gpio_show(struct seq_file *s, void *unused)
1700 unsigned i, j, gpio;
1702 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1703 struct gpio_bank *bank = gpio_bank + i;
1704 unsigned bankwidth = 16;
1707 if (bank_is_mpuio(bank))
1708 gpio = OMAP_MPUIO(0);
1709 else if (cpu_class_is_omap2() || cpu_is_omap730())
1712 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1713 unsigned irq, value, is_in, irqstat;
1715 if (!(bank->reserved_map & mask))
1718 irq = bank->virtual_irq_start + j;
1719 value = omap_get_gpio_datain(gpio);
1720 is_in = gpio_is_input(bank, mask);
1722 if (bank_is_mpuio(bank))
1723 seq_printf(s, "MPUIO %2d: ", j);
1725 seq_printf(s, "GPIO %3d: ", gpio);
1726 seq_printf(s, "%s %s",
1727 is_in ? "in " : "out",
1728 value ? "hi" : "lo");
1730 irqstat = irq_desc[irq].status;
1731 if (is_in && ((bank->suspend_wakeup & mask)
1732 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1733 char *trigger = NULL;
1735 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1736 case IRQ_TYPE_EDGE_FALLING:
1737 trigger = "falling";
1739 case IRQ_TYPE_EDGE_RISING:
1742 case IRQ_TYPE_EDGE_BOTH:
1743 trigger = "bothedge";
1745 case IRQ_TYPE_LEVEL_LOW:
1748 case IRQ_TYPE_LEVEL_HIGH:
1752 trigger = "(unspecified)";
1755 seq_printf(s, ", irq-%d %s%s",
1757 (bank->suspend_wakeup & mask)
1760 seq_printf(s, "\n");
1763 if (bank_is_mpuio(bank)) {
1764 seq_printf(s, "\n");
1771 static int dbg_gpio_open(struct inode *inode, struct file *file)
1773 return single_open(file, dbg_gpio_show, &inode->i_private);
1776 static const struct file_operations debug_fops = {
1777 .open = dbg_gpio_open,
1779 .llseek = seq_lseek,
1780 .release = single_release,
1783 static int __init omap_gpio_debuginit(void)
1785 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1786 NULL, NULL, &debug_fops);
1789 late_initcall(omap_gpio_debuginit);