arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * XXX handle crossbar/shared link difference for L3?
  13  * XXX these should be marked initdata for multi-OMAP kernels
  14  */
  15
  16 #include <linux/i2c-omap.h>
  17 #include <linux/platform_data/spi-omap2-mcspi.h>
  18
  19 #include <linux/omap-dma.h>
  20 #include <plat/dmtimer.h>
  21
  22 #include "omap_hwmod.h"
  23 #include "l3_2xxx.h"
  24 #include "l4_2xxx.h"
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "i2c.h"
  31 #include "mmc.h"
  32 #include "serial.h"
  33 #include "wd_timer.h"
  34
  35 /*
  36  * OMAP2420 hardware module integration data
  37  *
  38  * All of the data in this section should be autogeneratable from the
  39  * TI hardware database or other technical documentation.  Data that
  40  * is driver-specific or driver-kernel integration-specific belongs
  41  * elsewhere.
  42  */
  43
  44 /*
  45  * IP blocks
  46  */
  47
  48 /* IVA1 (IVA1) */
  49 static struct omap_hwmod_class iva1_hwmod_class = {
  50         .name           = "iva1",
  51 };
  52
  53 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
  54         { .name = "iva", .rst_shift = 8 },
  55 };
  56
  57 static struct omap_hwmod omap2420_iva_hwmod = {
  58         .name           = "iva",
  59         .class          = &iva1_hwmod_class,
  60         .clkdm_name     = "iva1_clkdm",
  61         .rst_lines      = omap2420_iva_resets,
  62         .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
  63         .main_clk       = "iva1_ifck",
  64 };
  65
  66 /* DSP */
  67 static struct omap_hwmod_class dsp_hwmod_class = {
  68         .name           = "dsp",
  69 };
  70
  71 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
  72         { .name = "logic", .rst_shift = 0 },
  73         { .name = "mmu", .rst_shift = 1 },
  74 };
  75
  76 static struct omap_hwmod omap2420_dsp_hwmod = {
  77         .name           = "dsp",
  78         .class          = &dsp_hwmod_class,
  79         .clkdm_name     = "dsp_clkdm",
  80         .rst_lines      = omap2420_dsp_resets,
  81         .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
  82         .main_clk       = "dsp_fck",
  83 };
  84
  85 /* I2C common */
  86 static struct omap_hwmod_class_sysconfig i2c_sysc = {
  87         .rev_offs       = 0x00,
  88         .sysc_offs      = 0x20,
  89         .syss_offs      = 0x10,
  90         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  91         .sysc_fields    = &omap_hwmod_sysc_type1,
  92 };
  93
  94 static struct omap_hwmod_class i2c_class = {
  95         .name           = "i2c",
  96         .sysc           = &i2c_sysc,
  97         .rev            = OMAP_I2C_IP_VERSION_1,
  98         .reset          = &omap_i2c_reset,
  99 };
 100
 101 static struct omap_i2c_dev_attr i2c_dev_attr = {
 102         .flags          = OMAP_I2C_FLAG_NO_FIFO |
 103                           OMAP_I2C_FLAG_SIMPLE_CLOCK |
 104                           OMAP_I2C_FLAG_16BIT_DATA_REG |
 105                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 106 };
 107
 108 /* I2C1 */
 109 static struct omap_hwmod omap2420_i2c1_hwmod = {
 110         .name           = "i2c1",
 111         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 112         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 113         .main_clk       = "i2c1_fck",
 114         .prcm           = {
 115                 .omap2 = {
 116                         .module_offs = CORE_MOD,
 117                         .prcm_reg_id = 1,
 118                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
 119                         .idlest_reg_id = 1,
 120                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
 121                 },
 122         },
 123         .class          = &i2c_class,
 124         .dev_attr       = &i2c_dev_attr,
 125         .flags          = HWMOD_16BIT_REG,
 126 };
 127
 128 /* I2C2 */
 129 static struct omap_hwmod omap2420_i2c2_hwmod = {
 130         .name           = "i2c2",
 131         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 132         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 133         .main_clk       = "i2c2_fck",
 134         .prcm           = {
 135                 .omap2 = {
 136                         .module_offs = CORE_MOD,
 137                         .prcm_reg_id = 1,
 138                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
 139                         .idlest_reg_id = 1,
 140                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
 141                 },
 142         },
 143         .class          = &i2c_class,
 144         .dev_attr       = &i2c_dev_attr,
 145         .flags          = HWMOD_16BIT_REG,
 146 };
 147
 148 /* dma attributes */
 149 static struct omap_dma_dev_attr dma_dev_attr = {
 150         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 151                                                 IS_CSSA_32 | IS_CDSA_32,
 152         .lch_count = 32,
 153 };
 154
 155 static struct omap_hwmod omap2420_dma_system_hwmod = {
 156         .name           = "dma",
 157         .class          = &omap2xxx_dma_hwmod_class,
 158         .mpu_irqs       = omap2_dma_system_irqs,
 159         .main_clk       = "core_l3_ck",
 160         .dev_attr       = &dma_dev_attr,
 161         .flags          = HWMOD_NO_IDLEST,
 162 };
 163
 164 /* mailbox */
 165 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
 166         { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
 167         { .name = "iva", .irq = 34 + OMAP_INTC_START, },
 168         { .irq = -1 },
 169 };
 170
 171 static struct omap_hwmod omap2420_mailbox_hwmod = {
 172         .name           = "mailbox",
 173         .class          = &omap2xxx_mailbox_hwmod_class,
 174         .mpu_irqs       = omap2420_mailbox_irqs,
 175         .main_clk       = "mailboxes_ick",
 176         .prcm           = {
 177                 .omap2 = {
 178                         .prcm_reg_id = 1,
 179                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
 180                         .module_offs = CORE_MOD,
 181                         .idlest_reg_id = 1,
 182                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 183                 },
 184         },
 185 };
 186
 187 /*
 188  * 'mcbsp' class
 189  * multi channel buffered serial port controller
 190  */
 191
 192 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
 193         .name = "mcbsp",
 194 };
 195
 196 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 197         { .role = "pad_fck", .clk = "mcbsp_clks" },
 198         { .role = "prcm_fck", .clk = "func_96m_ck" },
 199 };
 200
 201 /* mcbsp1 */
 202 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
 203         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
 204         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
 205         { .irq = -1 },
 206 };
 207
 208 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 209         .name           = "mcbsp1",
 210         .class          = &omap2420_mcbsp_hwmod_class,
 211         .mpu_irqs       = omap2420_mcbsp1_irqs,
 212         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
 213         .main_clk       = "mcbsp1_fck",
 214         .prcm           = {
 215                 .omap2 = {
 216                         .prcm_reg_id = 1,
 217                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
 218                         .module_offs = CORE_MOD,
 219                         .idlest_reg_id = 1,
 220                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
 221                 },
 222         },
 223         .opt_clks       = mcbsp_opt_clks,
 224         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 225 };
 226
 227 /* mcbsp2 */
 228 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
 229         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
 230         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
 231         { .irq = -1 },
 232 };
 233
 234 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
 235         .name           = "mcbsp2",
 236         .class          = &omap2420_mcbsp_hwmod_class,
 237         .mpu_irqs       = omap2420_mcbsp2_irqs,
 238         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
 239         .main_clk       = "mcbsp2_fck",
 240         .prcm           = {
 241                 .omap2 = {
 242                         .prcm_reg_id = 1,
 243                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
 244                         .module_offs = CORE_MOD,
 245                         .idlest_reg_id = 1,
 246                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
 247                 },
 248         },
 249         .opt_clks       = mcbsp_opt_clks,
 250         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 251 };
 252
 253 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
 254         .rev_offs       = 0x3c,
 255         .sysc_offs      = 0x64,
 256         .syss_offs      = 0x68,
 257         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 258         .sysc_fields    = &omap_hwmod_sysc_type1,
 259 };
 260
 261 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 262         .name   = "msdi",
 263         .sysc   = &omap2420_msdi_sysc,
 264         .reset  = &omap_msdi_reset,
 265 };
 266
 267 /* msdi1 */
 268 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
 269         { .irq = 83 + OMAP_INTC_START, },
 270         { .irq = -1 },
 271 };
 272
 273 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
 274         { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
 275         { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
 276         { .dma_req = -1 }
 277 };
 278
 279 static struct omap_hwmod omap2420_msdi1_hwmod = {
 280         .name           = "msdi1",
 281         .class          = &omap2420_msdi_hwmod_class,
 282         .mpu_irqs       = omap2420_msdi1_irqs,
 283         .sdma_reqs      = omap2420_msdi1_sdma_reqs,
 284         .main_clk       = "mmc_fck",
 285         .prcm           = {
 286                 .omap2 = {
 287                         .prcm_reg_id = 1,
 288                         .module_bit = OMAP2420_EN_MMC_SHIFT,
 289                         .module_offs = CORE_MOD,
 290                         .idlest_reg_id = 1,
 291                         .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
 292                 },
 293         },
 294         .flags          = HWMOD_16BIT_REG,
 295 };
 296
 297 /* HDQ1W/1-wire */
 298 static struct omap_hwmod omap2420_hdq1w_hwmod = {
 299         .name           = "hdq1w",
 300         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
 301         .main_clk       = "hdq_fck",
 302         .prcm           = {
 303                 .omap2 = {
 304                         .module_offs = CORE_MOD,
 305                         .prcm_reg_id = 1,
 306                         .module_bit = OMAP24XX_EN_HDQ_SHIFT,
 307                         .idlest_reg_id = 1,
 308                         .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
 309                 },
 310         },
 311         .class          = &omap2_hdq1w_class,
 312 };
 313
 314 /*
 315  * interfaces
 316  */
 317
 318 /* L4 CORE -> I2C1 interface */
 319 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 320         .master         = &omap2xxx_l4_core_hwmod,
 321         .slave          = &omap2420_i2c1_hwmod,
 322         .clk            = "i2c1_ick",
 323         .addr           = omap2_i2c1_addr_space,
 324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 325 };
 326
 327 /* L4 CORE -> I2C2 interface */
 328 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 329         .master         = &omap2xxx_l4_core_hwmod,
 330         .slave          = &omap2420_i2c2_hwmod,
 331         .clk            = "i2c2_ick",
 332         .addr           = omap2_i2c2_addr_space,
 333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 334 };
 335
 336 /* IVA <- L3 interface */
 337 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 338         .master         = &omap2xxx_l3_main_hwmod,
 339         .slave          = &omap2420_iva_hwmod,
 340         .clk            = "core_l3_ck",
 341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 342 };
 343
 344 /* DSP <- L3 interface */
 345 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
 346         .master         = &omap2xxx_l3_main_hwmod,
 347         .slave          = &omap2420_dsp_hwmod,
 348         .clk            = "dsp_ick",
 349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 350 };
 351
 352 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 353         {
 354                 .pa_start       = 0x48028000,
 355                 .pa_end         = 0x48028000 + SZ_1K - 1,
 356                 .flags          = ADDR_TYPE_RT
 357         },
 358         { }
 359 };
 360
 361 /* l4_wkup -> timer1 */
 362 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 363         .master         = &omap2xxx_l4_wkup_hwmod,
 364         .slave          = &omap2xxx_timer1_hwmod,
 365         .clk            = "gpt1_ick",
 366         .addr           = omap2420_timer1_addrs,
 367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 368 };
 369
 370 /* l4_wkup -> wd_timer2 */
 371 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 372         {
 373                 .pa_start       = 0x48022000,
 374                 .pa_end         = 0x4802207f,
 375                 .flags          = ADDR_TYPE_RT
 376         },
 377         { }
 378 };
 379
 380 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 381         .master         = &omap2xxx_l4_wkup_hwmod,
 382         .slave          = &omap2xxx_wd_timer2_hwmod,
 383         .clk            = "mpu_wdt_ick",
 384         .addr           = omap2420_wd_timer2_addrs,
 385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 386 };
 387
 388 /* l4_wkup -> gpio1 */
 389 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
 390         {
 391                 .pa_start       = 0x48018000,
 392                 .pa_end         = 0x480181ff,
 393                 .flags          = ADDR_TYPE_RT
 394         },
 395         { }
 396 };
 397
 398 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
 399         .master         = &omap2xxx_l4_wkup_hwmod,
 400         .slave          = &omap2xxx_gpio1_hwmod,
 401         .clk            = "gpios_ick",
 402         .addr           = omap2420_gpio1_addr_space,
 403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 404 };
 405
 406 /* l4_wkup -> gpio2 */
 407 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
 408         {
 409                 .pa_start       = 0x4801a000,
 410                 .pa_end         = 0x4801a1ff,
 411                 .flags          = ADDR_TYPE_RT
 412         },
 413         { }
 414 };
 415
 416 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
 417         .master         = &omap2xxx_l4_wkup_hwmod,
 418         .slave          = &omap2xxx_gpio2_hwmod,
 419         .clk            = "gpios_ick",
 420         .addr           = omap2420_gpio2_addr_space,
 421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 422 };
 423
 424 /* l4_wkup -> gpio3 */
 425 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
 426         {
 427                 .pa_start       = 0x4801c000,
 428                 .pa_end         = 0x4801c1ff,
 429                 .flags          = ADDR_TYPE_RT
 430         },
 431         { }
 432 };
 433
 434 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
 435         .master         = &omap2xxx_l4_wkup_hwmod,
 436         .slave          = &omap2xxx_gpio3_hwmod,
 437         .clk            = "gpios_ick",
 438         .addr           = omap2420_gpio3_addr_space,
 439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 440 };
 441
 442 /* l4_wkup -> gpio4 */
 443 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
 444         {
 445                 .pa_start       = 0x4801e000,
 446                 .pa_end         = 0x4801e1ff,
 447                 .flags          = ADDR_TYPE_RT
 448         },
 449         { }
 450 };
 451
 452 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
 453         .master         = &omap2xxx_l4_wkup_hwmod,
 454         .slave          = &omap2xxx_gpio4_hwmod,
 455         .clk            = "gpios_ick",
 456         .addr           = omap2420_gpio4_addr_space,
 457         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 458 };
 459
 460 /* dma_system -> L3 */
 461 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
 462         .master         = &omap2420_dma_system_hwmod,
 463         .slave          = &omap2xxx_l3_main_hwmod,
 464         .clk            = "core_l3_ck",
 465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 466 };
 467
 468 /* l4_core -> dma_system */
 469 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
 470         .master         = &omap2xxx_l4_core_hwmod,
 471         .slave          = &omap2420_dma_system_hwmod,
 472         .clk            = "sdma_ick",
 473         .addr           = omap2_dma_system_addrs,
 474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 475 };
 476
 477 /* l4_core -> mailbox */
 478 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
 479         .master         = &omap2xxx_l4_core_hwmod,
 480         .slave          = &omap2420_mailbox_hwmod,
 481         .addr           = omap2_mailbox_addrs,
 482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 483 };
 484
 485 /* l4_core -> mcbsp1 */
 486 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
 487         .master         = &omap2xxx_l4_core_hwmod,
 488         .slave          = &omap2420_mcbsp1_hwmod,
 489         .clk            = "mcbsp1_ick",
 490         .addr           = omap2_mcbsp1_addrs,
 491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 492 };
 493
 494 /* l4_core -> mcbsp2 */
 495 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
 496         .master         = &omap2xxx_l4_core_hwmod,
 497         .slave          = &omap2420_mcbsp2_hwmod,
 498         .clk            = "mcbsp2_ick",
 499         .addr           = omap2xxx_mcbsp2_addrs,
 500         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 501 };
 502
 503 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
 504         {
 505                 .pa_start       = 0x4809c000,
 506                 .pa_end         = 0x4809c000 + SZ_128 - 1,
 507                 .flags          = ADDR_TYPE_RT,
 508         },
 509         { }
 510 };
 511
 512 /* l4_core -> msdi1 */
 513 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
 514         .master         = &omap2xxx_l4_core_hwmod,
 515         .slave          = &omap2420_msdi1_hwmod,
 516         .clk            = "mmc_ick",
 517         .addr           = omap2420_msdi1_addrs,
 518         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 519 };
 520
 521 /* l4_core -> hdq1w interface */
 522 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
 523         .master         = &omap2xxx_l4_core_hwmod,
 524         .slave          = &omap2420_hdq1w_hwmod,
 525         .clk            = "hdq_ick",
 526         .addr           = omap2_hdq1w_addr_space,
 527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 528         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 529 };
 530
 531
 532 /* l4_wkup -> 32ksync_counter */
 533 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
 534         {
 535                 .pa_start       = 0x48004000,
 536                 .pa_end         = 0x4800401f,
 537                 .flags          = ADDR_TYPE_RT
 538         },
 539         { }
 540 };
 541
 542 static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
 543         {
 544                 .pa_start       = 0x6800a000,
 545                 .pa_end         = 0x6800afff,
 546                 .flags          = ADDR_TYPE_RT
 547         },
 548         { }
 549 };
 550
 551 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
 552         .master         = &omap2xxx_l4_wkup_hwmod,
 553         .slave          = &omap2xxx_counter_32k_hwmod,
 554         .clk            = "sync_32k_ick",
 555         .addr           = omap2420_counter_32k_addrs,
 556         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 557 };
 558
 559 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
 560         .master         = &omap2xxx_l3_main_hwmod,
 561         .slave          = &omap2xxx_gpmc_hwmod,
 562         .clk            = "core_l3_ck",
 563         .addr           = omap2420_gpmc_addrs,
 564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 565 };
 566
 567 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 568         &omap2xxx_l3_main__l4_core,
 569         &omap2xxx_mpu__l3_main,
 570         &omap2xxx_dss__l3,
 571         &omap2xxx_l4_core__mcspi1,
 572         &omap2xxx_l4_core__mcspi2,
 573         &omap2xxx_l4_core__l4_wkup,
 574         &omap2_l4_core__uart1,
 575         &omap2_l4_core__uart2,
 576         &omap2_l4_core__uart3,
 577         &omap2420_l4_core__i2c1,
 578         &omap2420_l4_core__i2c2,
 579         &omap2420_l3__iva,
 580         &omap2420_l3__dsp,
 581         &omap2420_l4_wkup__timer1,
 582         &omap2xxx_l4_core__timer2,
 583         &omap2xxx_l4_core__timer3,
 584         &omap2xxx_l4_core__timer4,
 585         &omap2xxx_l4_core__timer5,
 586         &omap2xxx_l4_core__timer6,
 587         &omap2xxx_l4_core__timer7,
 588         &omap2xxx_l4_core__timer8,
 589         &omap2xxx_l4_core__timer9,
 590         &omap2xxx_l4_core__timer10,
 591         &omap2xxx_l4_core__timer11,
 592         &omap2xxx_l4_core__timer12,
 593         &omap2420_l4_wkup__wd_timer2,
 594         &omap2xxx_l4_core__dss,
 595         &omap2xxx_l4_core__dss_dispc,
 596         &omap2xxx_l4_core__dss_rfbi,
 597         &omap2xxx_l4_core__dss_venc,
 598         &omap2420_l4_wkup__gpio1,
 599         &omap2420_l4_wkup__gpio2,
 600         &omap2420_l4_wkup__gpio3,
 601         &omap2420_l4_wkup__gpio4,
 602         &omap2420_dma_system__l3,
 603         &omap2420_l4_core__dma_system,
 604         &omap2420_l4_core__mailbox,
 605         &omap2420_l4_core__mcbsp1,
 606         &omap2420_l4_core__mcbsp2,
 607         &omap2420_l4_core__msdi1,
 608         &omap2xxx_l4_core__rng,
 609         &omap2420_l4_core__hdq1w,
 610         &omap2420_l4_wkup__counter_32k,
 611         &omap2420_l3__gpmc,
 612         NULL,
 613 };
 614
 615 int __init omap2420_hwmod_init(void)
 616 {
 617         omap_hwmod_init();
 618         return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 619 }