2 * linux/arch/arm/mach-omap2/cpuidle34xx.c
4 * OMAP3 CPU IDLE Routines
6 * Copyright (C) 2008 Texas Instruments, Inc.
7 * Rajendra Nayak <rnayak@ti.com>
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Karthik Dasu <karthik-dp@ti.com>
12 * Copyright (C) 2006 Nokia Corporation
13 * Tony Lindgren <tony@atomide.com>
15 * Copyright (C) 2005 Texas Instruments, Inc.
16 * Richard Woodruff <r-woodruff2@ti.com>
18 * Based on pm.c for omap2
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License version 2 as
22 * published by the Free Software Foundation.
25 #include <linux/sched.h>
26 #include <linux/cpuidle.h>
27 #include <linux/export.h>
29 #include <plat/prcm.h>
30 #include <plat/irqs.h>
31 #include "powerdomain.h"
32 #include "clockdomain.h"
33 #include <plat/serial.h>
38 #ifdef CONFIG_CPU_IDLE
41 * The latencies/thresholds for various C states have
42 * to be configured from the respective board files.
43 * These are some default values (which might not provide
44 * the best power savings) used on boards which do not
45 * pass these details from the board file.
47 static struct cpuidle_params cpuidle_params_table[] = {
55 {1500 + 1800, 4000, 1},
57 {2500 + 7500, 12000, 1},
59 {3000 + 8500, 15000, 1},
61 {10000 + 30000, 300000, 1},
63 #define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
65 /* Mach specific information to be recorded in the C-state driver_data */
66 struct omap3_idle_statedata {
71 struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
73 struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
75 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
76 struct clockdomain *clkdm)
78 clkdm_allow_idle(clkdm);
82 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
83 struct clockdomain *clkdm)
85 clkdm_deny_idle(clkdm);
90 * omap3_enter_idle - Programs OMAP3 to enter the specified state
91 * @dev: cpuidle device
92 * @drv: cpuidle driver
93 * @index: the index of state to be entered
95 * Called from the CPUidle framework to program the device to the
96 * specified target state selected by the governor.
98 static int omap3_enter_idle(struct cpuidle_device *dev,
99 struct cpuidle_driver *drv,
102 struct omap3_idle_statedata *cx =
103 cpuidle_get_statedata(&dev->states_usage[index]);
104 struct timespec ts_preidle, ts_postidle, ts_idle;
105 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
108 /* Used to keep track of the total time in idle */
109 getnstimeofday(&ts_preidle);
114 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
115 pwrdm_set_next_pwrst(core_pd, core_state);
117 if (omap_irq_pending() || need_resched())
118 goto return_sleep_time;
120 /* Deny idle for C1 */
122 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
123 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
126 /* Execute ARM wfi */
129 /* Re-allow idle for C1 */
131 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
132 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
136 getnstimeofday(&ts_postidle);
137 ts_idle = timespec_sub(ts_postidle, ts_preidle);
142 idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
145 /* Update cpuidle counters */
146 dev->last_residency = idle_time;
152 * next_valid_state - Find next valid C-state
153 * @dev: cpuidle device
154 * @drv: cpuidle driver
155 * @index: Index of currently selected c-state
157 * If the state corresponding to index is valid, index is returned back
158 * to the caller. Else, this function searches for a lower c-state which is
159 * still valid (as defined in omap3_power_states[]) and returns its index.
161 * A state is valid if the 'valid' field is enabled and
162 * if it satisfies the enable_off_mode condition.
164 static int next_valid_state(struct cpuidle_device *dev,
165 struct cpuidle_driver *drv,
168 struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
169 struct cpuidle_state *curr = &drv->states[index];
170 struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
171 u32 mpu_deepest_state = PWRDM_POWER_RET;
172 u32 core_deepest_state = PWRDM_POWER_RET;
175 if (enable_off_mode) {
176 mpu_deepest_state = PWRDM_POWER_OFF;
178 * Erratum i583: valable for ES rev < Es1.2 on 3630.
179 * CORE OFF mode is not supported in a stable form, restrict
180 * instead the CORE state to RET.
182 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
183 core_deepest_state = PWRDM_POWER_OFF;
186 /* Check if current state is valid */
188 (cx->mpu_state >= mpu_deepest_state) &&
189 (cx->core_state >= core_deepest_state)) {
192 int idx = OMAP3_NUM_STATES - 1;
194 /* Reach the current state starting at highest C-state */
195 for (; idx >= 0; idx--) {
196 if (&drv->states[idx] == curr) {
202 /* Should never hit this condition */
203 WARN_ON(next_index == -1);
206 * Drop to next valid state.
207 * Start search from the next (lower) state.
210 for (; idx >= 0; idx--) {
211 cx = cpuidle_get_statedata(&dev->states_usage[idx]);
213 (cx->mpu_state >= mpu_deepest_state) &&
214 (cx->core_state >= core_deepest_state)) {
220 * C1 is always valid.
221 * So, no need to check for 'next_index == -1' outside
230 * omap3_enter_idle_bm - Checks for any bus activity
231 * @dev: cpuidle device
232 * @drv: cpuidle driver
233 * @index: array index of target state to be programmed
235 * This function checks for any pending activity and then programs
236 * the device to the specified or a safer state.
238 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
239 struct cpuidle_driver *drv,
243 u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
244 struct omap3_idle_statedata *cx;
247 if (!omap3_can_sleep()) {
248 new_state_idx = drv->safe_state_index;
253 * Prevent idle completely if CAM is active.
254 * CAM does not have wakeup capability in OMAP3.
256 cam_state = pwrdm_read_pwrst(cam_pd);
257 if (cam_state == PWRDM_POWER_ON) {
258 new_state_idx = drv->safe_state_index;
263 * FIXME: we currently manage device-specific idle states
264 * for PER and CORE in combination with CPU-specific
265 * idle states. This is wrong, and device-specific
266 * idle management needs to be separated out into
271 * Prevent PER off if CORE is not in retention or off as this
272 * would disable PER wakeups completely.
274 cx = cpuidle_get_statedata(&dev->states_usage[index]);
275 core_next_state = cx->core_state;
276 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
277 if ((per_next_state == PWRDM_POWER_OFF) &&
278 (core_next_state > PWRDM_POWER_RET))
279 per_next_state = PWRDM_POWER_RET;
281 /* Are we changing PER target state? */
282 if (per_next_state != per_saved_state)
283 pwrdm_set_next_pwrst(per_pd, per_next_state);
285 new_state_idx = next_valid_state(dev, drv, index);
288 ret = omap3_enter_idle(dev, drv, new_state_idx);
290 /* Restore original PER state if it was modified */
291 if (per_next_state != per_saved_state)
292 pwrdm_set_next_pwrst(per_pd, per_saved_state);
297 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
299 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
303 if (!cpuidle_board_params)
306 for (i = 0; i < OMAP3_NUM_STATES; i++) {
307 cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
308 cpuidle_params_table[i].exit_latency =
309 cpuidle_board_params[i].exit_latency;
310 cpuidle_params_table[i].target_residency =
311 cpuidle_board_params[i].target_residency;
316 struct cpuidle_driver omap3_idle_driver = {
317 .name = "omap3_idle",
318 .owner = THIS_MODULE,
321 /* Helper to fill the C-state common data*/
322 static inline void _fill_cstate(struct cpuidle_driver *drv,
323 int idx, const char *descr)
325 struct cpuidle_state *state = &drv->states[idx];
327 state->exit_latency = cpuidle_params_table[idx].exit_latency;
328 state->target_residency = cpuidle_params_table[idx].target_residency;
329 state->flags = CPUIDLE_FLAG_TIME_VALID;
330 state->enter = omap3_enter_idle_bm;
331 sprintf(state->name, "C%d", idx + 1);
332 strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
336 /* Helper to register the driver_data */
337 static inline struct omap3_idle_statedata *_fill_cstate_usage(
338 struct cpuidle_device *dev,
341 struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
342 struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
344 cx->valid = cpuidle_params_table[idx].valid;
345 cpuidle_set_statedata(state_usage, cx);
351 * omap3_idle_init - Init routine for OMAP3 idle
353 * Registers the OMAP3 specific cpuidle driver to the cpuidle
354 * framework with the valid set of states.
356 int __init omap3_idle_init(void)
358 struct cpuidle_device *dev;
359 struct cpuidle_driver *drv = &omap3_idle_driver;
360 struct omap3_idle_statedata *cx;
362 mpu_pd = pwrdm_lookup("mpu_pwrdm");
363 core_pd = pwrdm_lookup("core_pwrdm");
364 per_pd = pwrdm_lookup("per_pwrdm");
365 cam_pd = pwrdm_lookup("cam_pwrdm");
368 drv->safe_state_index = -1;
369 dev = &per_cpu(omap3_idle_dev, smp_processor_id());
371 /* C1 . MPU WFI + Core active */
372 _fill_cstate(drv, 0, "MPU ON + CORE ON");
373 (&drv->states[0])->enter = omap3_enter_idle;
374 drv->safe_state_index = 0;
375 cx = _fill_cstate_usage(dev, 0);
376 cx->valid = 1; /* C1 is always valid */
377 cx->mpu_state = PWRDM_POWER_ON;
378 cx->core_state = PWRDM_POWER_ON;
380 /* C2 . MPU WFI + Core inactive */
381 _fill_cstate(drv, 1, "MPU ON + CORE ON");
382 cx = _fill_cstate_usage(dev, 1);
383 cx->mpu_state = PWRDM_POWER_ON;
384 cx->core_state = PWRDM_POWER_ON;
386 /* C3 . MPU CSWR + Core inactive */
387 _fill_cstate(drv, 2, "MPU RET + CORE ON");
388 cx = _fill_cstate_usage(dev, 2);
389 cx->mpu_state = PWRDM_POWER_RET;
390 cx->core_state = PWRDM_POWER_ON;
392 /* C4 . MPU OFF + Core inactive */
393 _fill_cstate(drv, 3, "MPU OFF + CORE ON");
394 cx = _fill_cstate_usage(dev, 3);
395 cx->mpu_state = PWRDM_POWER_OFF;
396 cx->core_state = PWRDM_POWER_ON;
398 /* C5 . MPU RET + Core RET */
399 _fill_cstate(drv, 4, "MPU RET + CORE RET");
400 cx = _fill_cstate_usage(dev, 4);
401 cx->mpu_state = PWRDM_POWER_RET;
402 cx->core_state = PWRDM_POWER_RET;
404 /* C6 . MPU OFF + Core RET */
405 _fill_cstate(drv, 5, "MPU OFF + CORE RET");
406 cx = _fill_cstate_usage(dev, 5);
407 cx->mpu_state = PWRDM_POWER_OFF;
408 cx->core_state = PWRDM_POWER_RET;
410 /* C7 . MPU OFF + Core OFF */
411 _fill_cstate(drv, 6, "MPU OFF + CORE OFF");
412 cx = _fill_cstate_usage(dev, 6);
414 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
415 * enable OFF mode in a stable form for previous revisions.
416 * We disable C7 state as a result.
418 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
420 pr_warn("%s: core off state C7 disabled due to i583\n",
423 cx->mpu_state = PWRDM_POWER_OFF;
424 cx->core_state = PWRDM_POWER_OFF;
426 drv->state_count = OMAP3_NUM_STATES;
427 cpuidle_register_driver(&omap3_idle_driver);
429 dev->state_count = OMAP3_NUM_STATES;
430 if (cpuidle_register_device(dev)) {
431 printk(KERN_ERR "%s: CPUidle register device failed\n",
439 int __init omap3_idle_init(void)
443 #endif /* CONFIG_CPU_IDLE */