1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
8 interrupt-parent = <&gic>;
10 /* external reference clock */
11 clk_refclk: clk-refclk {
12 compatible = "fixed-clock";
14 clock-frequency = <25000000>;
15 clock-output-names = "refclk";
19 rstc: reset-controller@f0801000 {
20 compatible = "nuvoton,npcm845-reset", "syscon",
22 reg = <0x0 0xf0801000 0x0 0xC4>;
26 clk: clock-controller@f0801000 {
27 compatible = "nuvoton,npcm845-clk", "syscon";
30 reg = <0x0 0xf0801000 0x0 0x1000>;
31 clock-names = "refclk";
32 clocks = <&clk_refclk>;
36 device_type = "network";
37 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
38 reg = <0x0 0xf0802000 0x0 0x2000>,
39 <0x0 0xf0780000 0x0 0x200>;
40 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
41 interrupt-names = "macirq";
42 clocks = <&clk NPCM8XX_CLK_AHB>;
43 clock-names = "stmmaceth";
44 pinctrl-names = "default";
45 pinctrl-0 = <&rg1mdio_pins>;
46 resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC1>;
51 device_type = "network";
52 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
53 reg = <0x0 0xf0804000 0x0 0x2000>;
54 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
55 interrupt-names = "macirq";
56 clocks = <&clk NPCM8XX_CLK_AHB>;
57 clock-names = "stmmaceth";
58 pinctrl-names = "default";
59 pinctrl-0 = <&rg2_pins
61 resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_GMAC2>;
66 device_type = "network";
67 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
68 reg = <0x0 0xf0806000 0x0 0x2000>;
69 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-names = "macirq";
71 clocks = <&clk NPCM8XX_CLK_AHB>;
72 clock-names = "stmmaceth";
73 pinctrl-names = "default";
77 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC3>;
82 device_type = "network";
83 compatible = "nuvoton,npcm-dwmac", "st,stm32-dwmac";
84 reg = <0x0 0xf0808000 0x0 0x2000>;
85 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-names = "macirq";
87 clocks = <&clk NPCM8XX_CLK_AHB>;
88 clock-names = "stmmaceth";
89 pinctrl-names = "default";
93 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_GMAC4>;
98 compatible = "nuvoton,npcm845-ehci";
99 reg = <0x0 0xf0828100 0x0 0x1000>;
100 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
101 resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>;
105 ehci2: usb@f082a100 {
106 compatible = "nuvoton,npcm845-ehci";
107 reg = <0x0 0xf082a100 0x0 0x1000>;
108 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
109 resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>;
113 ohci1: usb@f0829000 {
114 compatible = "nuvoton,npcm845-ohci";
115 reg = <0x0 0xF0829000 0x0 0x1000>;
116 resets = <&rstc NPCM8XX_RESET_IPSRST2 NPCM8XX_RESET_USBH1>;
120 ohci2: usb@f082b000 {
121 compatible = "nuvoton,npcm845-ohci";
122 reg = <0x0 0xF082B000 0x0 0x1000>;
123 resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBH2>;
128 compatible = "simple-bus";
129 #address-cells = <1>;
133 compatible = "nuvoton,npcm845-usb-phy";
136 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY1>;
140 compatible = "nuvoton,npcm845-usb-phy";
143 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_USBPHY2>;
147 compatible = "nuvoton,npcm845-usb-phy";
150 resets = <&rstc NPCM8XX_RESET_IPSRST4 NPCM8XX_RESET_USBPHY3>;
156 compatible = "nuvoton,npcm845-udc";
157 reg = <0x0 0xf0830100 0x0 0x100
158 0x0 0xfffb0000 0x0 0x800>;
159 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clk NPCM8XX_CLK_SU>;
161 clock-names = "clk_usb_bridge";
162 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC0>;
167 compatible = "nuvoton,npcm845-udc";
168 reg = <0x0 0xf0831100 0x0 0x100
169 0x0 0xfffb0800 0x0 0x800>;
170 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&clk NPCM8XX_CLK_SU>;
172 clock-names = "clk_usb_bridge";
173 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC1>;
178 compatible = "nuvoton,npcm845-udc";
179 reg = <0x0 0xf0832100 0x0 0x100
180 0x0 0xfffb1000 0x0 0x800>;
181 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&clk NPCM8XX_CLK_SU>;
183 clock-names = "clk_usb_bridge";
184 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC2>;
189 compatible = "nuvoton,npcm845-udc";
190 reg = <0x0 0xf0833100 0x0 0x100
191 0x0 0xfffb1800 0x0 0x800>;
192 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&clk NPCM8XX_CLK_SU>;
194 clock-names = "clk_usb_bridge";
195 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC3>;
200 compatible = "nuvoton,npcm845-udc";
201 reg = <0x0 0xf0834100 0x0 0x100
202 0x0 0xfffb2000 0x0 0x800>;
203 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&clk NPCM8XX_CLK_SU>;
205 clock-names = "clk_usb_bridge";
206 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC4>;
211 compatible = "nuvoton,npcm845-udc";
212 reg = <0x0 0xf0835100 0x0 0x100
213 0x0 0xfffb2800 0x0 0x800>;
214 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&clk NPCM8XX_CLK_SU>;
216 clock-names = "clk_usb_bridge";
217 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC5>;
222 compatible = "nuvoton,npcm845-udc";
223 reg = <0x0 0xf0836100 0x0 0x100
224 0x0 0xfffb3000 0x0 0x800>;
225 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clk NPCM8XX_CLK_SU>;
227 clock-names = "clk_usb_bridge";
228 resets = <&rstc NPCM8XX_RESET_IPSRST1 NPCM8XX_RESET_UDC6>;
233 compatible = "nuvoton,npcm845-udc";
234 reg = <0x0 0xf0837100 0x0 0x100
235 0x0 0xfffb3800 0x0 0x800>;
236 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&clk NPCM8XX_CLK_SU>;
238 clock-names = "clk_usb_bridge";
239 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC7>;
244 compatible = "nuvoton,npcm845-udc";
245 reg = <0x0 0xf0838100 0x0 0x100
246 0x0 0xfffb4000 0x0 0x800>;
247 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clk NPCM8XX_CLK_SU>;
249 clock-names = "clk_usb_bridge";
250 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC8>;
255 compatible = "nuvoton,npcm845-udc";
256 reg = <0x0 0xf0839100 0x0 0x100
257 0x0 0xfffb4800 0x0 0x800>;
258 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clk NPCM8XX_CLK_SU>;
260 clock-names = "clk_usb_bridge";
261 resets = <&rstc NPCM8XX_RESET_IPSRST3 NPCM8XX_RESET_UDC9>;
266 compatible = "nuvoton,npcm845-aes";
267 reg = <0x0 0xf0858000 0x0 0x1000>,
268 <0x0 0xf0851000 0x0 0x1000>;
270 clocks = <&clk NPCM8XX_CLK_AHB>;
271 clock-names = "clk_ahb";
275 compatible = "nuvoton,npcm845-sha";
276 reg = <0x0 0xf085a000 0x0 0x1000>;
278 clocks = <&clk NPCM8XX_CLK_AHB>;
279 clock-names = "clk_ahb";
284 compatible = "nuvoton,npcm845-uart";
286 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
287 clock-frequency = <24000000>;
291 serial1: serial@1000 {
292 compatible = "nuvoton,npcm845-uart";
293 reg = <0x1000 0x1000>;
294 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
298 serial2: serial@2000 {
299 compatible = "nuvoton,npcm845-uart";
300 reg = <0x2000 0x1000>;
301 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
305 serial3: serial@3000 {
306 compatible = "nuvoton,npcm845-uart";
307 reg = <0x3000 0x1000>;
308 clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
312 serial4: serial@4000 {
313 compatible = "nuvoton,npcm845-uart";
314 reg = <0x4000 0x1000>;
315 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
319 serial5: serial@5000 {
320 compatible = "nuvoton,npcm845-uart";
321 reg = <0x5000 0x1000>;
322 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
326 serial6: serial@6000 {
327 compatible = "nuvoton,npcm845-uart";
328 reg = <0x6000 0x1000>;
329 clocks = <&clk NPCM8XX_CLK_UART2>, <&clk NPCM8XX_CLK_PLL2DIV2>;
330 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
335 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
336 reg = <0x10000 0xB0>;
339 gpio-bank-name = "gpio0";
343 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
344 reg = <0x11000 0xB0>;
347 gpio-bank-name = "gpio1";
351 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
352 reg = <0x12000 0xB0>;
355 gpio-bank-name = "gpio2";
359 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
360 reg = <0x13000 0xB0>;
363 gpio-bank-name = "gpio3";
367 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
368 reg = <0x14000 0xB0>;
371 gpio-bank-name = "gpio4";
375 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
376 reg = <0x15000 0xB0>;
379 gpio-bank-name = "gpio5";
383 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
384 reg = <0x16000 0xB0>;
387 gpio-bank-name = "gpio6";
391 compatible = "nuvoton,npcm-gpio", "nuvoton,npcm845-gpio";
392 reg = <0x17000 0xB0>;
395 gpio-bank-name = "gpio7";
399 compatible = "nuvoton,npcm845-rng";
405 compatible = "nuvoton,npcm845-otp";
406 reg = <0x189000 0x1000>;
412 pinctrl: pinctrl@f0800000 {
413 compatible = "nuvoton,npcm845-pinctrl", "syscon", "simple-mfd";
414 reg = <0x0 0xf0010000 0x0 0x8000>;
416 syscon-rst = <&rstc>;
419 iox1_pins: iox1-pins {
423 iox2_pins: iox2-pins {
427 smb1d_pins: smb1d-pins {
431 smb2d_pins: smb2d-pins {
435 lkgpo1_pins: lkgpo1-pins {
439 lkgpo2_pins: lkgpo2-pins {
443 ioxh_pins: ioxh-pins {
447 gspi_pins: gspi-pins {
451 smb5b_pins: smb5b-pins {
455 smb5c_pins: smb5c-pins {
459 lkgpo0_pins: lkgpo0-pins {
463 pspi_pins: pspi-pins {
467 vgadig_pins: vgadig-pins {
479 smb4b_pins: smb4b-pins {
483 smb4c_pins: smb4c-pins {
487 smb15_pins: smb15-pins {
491 smb16_pins: smb16-pins {
495 smb17_pins: smb17-pins {
499 smb18_pins: smb18-pins {
503 smb19_pins: smb19-pins {
507 smb20_pins: smb20-pins {
511 smb21_pins: smb21-pins {
515 smb22_pins: smb22-pins {
519 smb23_pins: smb23-pins {
523 smb4d_pins: smb4d-pins {
527 smb14_pins: smb14-pins {
531 smb5_pins: smb5-pins {
535 smb4_pins: smb4-pins {
539 smb3_pins: smb3-pins {
543 spi0cs1_pins: spi0cs1-pins {
545 function = "spi0cs1";
547 spi0cs2_pins: spi0cs2-pins {
549 function = "spi0cs2";
551 spi0cs3_pins: spi0cs3-pins {
553 function = "spi0cs3";
555 smb3c_pins: smb3c-pins {
559 smb3b_pins: smb3b-pins {
563 hsi1a_pins: hsi1a-pins {
567 hsi1b_pins: hsi1b-pins {
571 hsi1c_pins: hsi1c-pins {
575 hsi2a_pins: hsi2a-pins {
579 hsi2b_pins: hsi2b-pins {
583 hsi2c_pins: hsi2c-pins {
587 bmcuart0a_pins: bmcuart0a-pins {
588 groups = "bmcuart0a";
589 function = "bmcuart0a";
591 bmcuart0b_pins: bmcuart0b-pins {
592 groups = "bmcuart0b";
593 function = "bmcuart0b";
595 bmcuart1_pins: bmcuart1-pins {
597 function = "bmcuart1";
611 r1err_pins: r1err-pins {
615 r1md_pins: r1md-pins {
619 r1oen_pins: r1oen-pins {
623 r1en_pins: r1en-pins {
627 r2oen_pins: r2oen-pins {
631 r2en_pins: r2en-pins {
635 rmii3_pins: rmii3_pins {
639 r3oen_pins: r3oen-pins {
643 r3en_pins: r3en-pins {
647 smb3d_pins: smb3d-pins {
651 fanin0_pins: fanin0-pins {
655 fanin1_pins: fanin1-pins {
659 fanin2_pins: fanin2-pins {
663 fanin3_pins: fanin3-pins {
667 fanin4_pins: fanin4-pins {
671 fanin5_pins: fanin5-pins {
675 fanin6_pins: fanin6-pins {
679 fanin7_pins: fanin7-pins {
683 fanin8_pins: fanin8-pins {
687 fanin9_pins: fanin9-pins {
691 fanin10_pins: fanin10-pins {
693 function = "fanin10";
695 fanin11_pins: fanin11-pins {
697 function = "fanin11";
699 fanin12_pins: fanin12-pins {
701 function = "fanin12";
703 fanin13_pins: fanin13-pins {
705 function = "fanin13";
707 fanin14_pins: fanin14-pins {
709 function = "fanin14";
711 fanin15_pins: fanin15-pins {
713 function = "fanin15";
715 pwm0_pins: pwm0-pins {
719 pwm1_pins: pwm1-pins {
723 pwm2_pins: pwm2-pins {
727 pwm3_pins: pwm3-pins {
735 r2err_pins: r2err-pins {
739 r2md_pins: r2md-pins {
743 r3rxer_pins: r3rxer_pins {
747 ga20kbc_pins: ga20kbc-pins {
749 function = "ga20kbc";
751 smb5d_pins: smb5d-pins {
759 espi_pins: espi-pins {
767 rg1mdio_pins: rg1mdio-pins {
769 function = "rg1mdio";
779 i3c0_pins: i3c0-pins {
783 i3c1_pins: i3c1-pins {
787 i3c2_pins: i3c2-pins {
791 i3c3_pins: i3c3-pins {
795 i3c4_pins: i3c4-pins {
799 i3c5_pins: i3c5-pins {
803 smb0_pins: smb0-pins {
807 smb1_pins: smb1-pins {
811 smb2_pins: smb2-pins {
815 smb2c_pins: smb2c-pins {
819 smb2b_pins: smb2b-pins {
823 smb1c_pins: smb1c-pins {
827 smb1b_pins: smb1b-pins {
831 smb8_pins: smb8-pins {
835 smb9_pins: smb9-pins {
839 smb10_pins: smb10-pins {
843 smb11_pins: smb11-pins {
851 sd1pwr_pins: sd1pwr-pins {
855 pwm4_pins: pwm4-pins {
859 pwm5_pins: pwm5-pins {
863 pwm6_pins: pwm6-pins {
867 pwm7_pins: pwm7-pins {
871 pwm8_pins: pwm8-pins {
875 pwm9_pins: pwm9-pins {
879 pwm10_pins: pwm10-pins {
883 pwm11_pins: pwm11-pins {
887 mmc8_pins: mmc8-pins {
895 mmcwp_pins: mmcwp-pins {
899 mmccd_pins: mmccd-pins {
903 mmcrst_pins: mmcrst-pins {
907 clkout_pins: clkout-pins {
911 serirq_pins: serirq-pins {
915 scipme_pins: scipme-pins {
923 smb6_pins: smb6-pins {
927 smb7_pins: smb7-pins {
931 spi1_pins: spi1-pins {
935 spi1d23_pins: spi1d23-pins {
937 function = "spi1d23";
939 faninx_pins: faninx-pins {
947 spi3_pins: spi3-pins {
951 spi3cs1_pins: spi3cs1-pins {
953 function = "spi3cs1";
955 spi3quad_pins: spi3quad-pins {
957 function = "spi3quad";
959 spi3cs2_pins: spi3cs2-pins {
961 function = "spi3cs2";
963 spi3cs3_pins: spi3cs3-pins {
965 function = "spi3cs3";
967 nprd_smi_pins: nprd-smi-pins {
969 function = "nprd_smi";
971 smb0b_pins: smb0b-pins {
975 smb0c_pins: smb0c-pins {
979 smb0den_pins: smb0den-pins {
981 function = "smb0den";
983 smb0d_pins: smb0d-pins {
987 rg2mdio_pins: rg2mdio-pins {
989 function = "rg2mdio";
991 rg2refck_pins: rg2refck-pins {
993 function = "rg2refck";
995 wdog1_pins: wdog1-pins {
999 wdog2_pins: wdog2-pins {
1003 smb12_pins: smb12-pins {
1007 smb13_pins: smb13-pins {
1011 spix_pins: spix-pins {
1015 spixcs1_pins: spixcs1-pins {
1017 function = "spixcs1";
1019 clkreq_pins: clkreq-pins {
1021 function = "clkreq";
1023 hgpio0_pins: hgpio0-pins {
1025 function = "hgpio0";
1027 hgpio1_pins: hgpio1-pins {
1029 function = "hgpio1";
1031 hgpio2_pins: hgpio2-pins {
1033 function = "hgpio2";
1035 hgpio3_pins: hgpio3-pins {
1037 function = "hgpio3";
1039 hgpio4_pins: hgpio4-pins {
1041 function = "hgpio4";
1043 hgpio5_pins: hgpio5-pins {
1045 function = "hgpio5";
1047 hgpio6_pins: hgpio6-pins {
1049 function = "hgpio6";
1051 hgpio7_pins: hgpio7-pins {
1053 function = "hgpio7";
1055 jtag2_pins: jtag2-pins {