arch/arm/dts/imx6-logicpd-baseboard.dtsi

   1 /*
   2  * Copyright 2018 Logic PD, Inc.
   3  * Based on SabreSD, Copyright 2016 Freescale Semiconductor, Inc.
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 / {
  45         keyboard {
  46                 compatible = "gpio-keys";
  47
  48                 btn0 {
  49                         gpios = <&pcf8575 0 GPIO_ACTIVE_LOW>;
  50                         label = "btn0";
  51                         linux,code = <KEY_WAKEUP>;
  52                         debounce-interval = <10>;
  53                         wakeup-source;
  54                 };
  55
  56                 btn1 {
  57                         gpios = <&pcf8575 1 GPIO_ACTIVE_LOW>;
  58                         label = "btn1";
  59                         linux,code = <KEY_WAKEUP>;
  60                         debounce-interval = <10>;
  61                         wakeup-source;
  62                 };
  63
  64                 btn2 {
  65                         gpios = <&pcf8575 2 GPIO_ACTIVE_LOW>;
  66                         label = "btn2";
  67                         linux,code = <KEY_WAKEUP>;
  68                         debounce-interval = <10>;
  69                         wakeup-source;
  70                 };
  71                 btn3 {
  72                         gpios = <&pcf8575 3 GPIO_ACTIVE_LOW>;
  73                         label = "btn3";
  74                         linux,code = <KEY_WAKEUP>;
  75                         debounce-interval = <10>;
  76                         wakeup-source;
  77                 };
  78
  79         };
  80
  81         leds {
  82                 compatible = "gpio-leds";
  83
  84                 gen_led0 {
  85                         label = "led0";
  86                         pinctrl-names = "default";
  87                         pinctrl-0 = <&pinctrl_led0>;
  88                         gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
  89                         linux,default-trigger = "cpu0";
  90                 };
  91
  92                 gen_led1 {
  93                         label = "led1";
  94                         gpios = <&pcf8575 8 GPIO_ACTIVE_HIGH>;
  95                 };
  96
  97                 gen_led2 {
  98                         label = "led2";
  99                         gpios = <&pcf8575 9 GPIO_ACTIVE_HIGH>;
 100                         linux,default-trigger = "heartbeat";
 101                 };
 102
 103                 gen_led3 {
 104                         label = "led3";
 105                         gpios = <&pcf8575 10 GPIO_ACTIVE_HIGH>;
 106                         linux,default-trigger = "default-on";
 107                 };
 108         };
 109
 110         reg_usb_otg_vbus: regulator-otg-vbus@0 {
 111                 compatible = "regulator-fixed";
 112                 regulator-name = "usb_otg_vbus";
 113                 regulator-min-microvolt = <5000000>;
 114                 regulator-max-microvolt = <5000000>;
 115                 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
 116                 enable-active-high;
 117         };
 118
 119         reg_usb_h1_vbus: regulator-usbh1vbus@1 {
 120                 compatible = "regulator-fixed";
 121                 regulator-name = "usb_h1_vbus";
 122                 regulator-min-microvolt = <5000000>;
 123                 regulator-max-microvolt = <5000000>;
 124         };
 125
 126         reg_3v3: regulator-3v3@2 {
 127                 pinctrl-names = "default";
 128                 pinctrl-0 = <&pinctrl_reg_3v3>;
 129                 compatible = "regulator-fixed";
 130                 regulator-name = "reg_3v3";
 131                 regulator-min-microvolt = <3300000>;
 132                 regulator-max-microvolt = <3300000>;
 133                 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 134                 enable-active-high;
 135                 regulator-always-on;
 136         };
 137
 138         reg_enet: regulator-ethernet@3 {
 139                 pinctrl-names = "default";
 140                 pinctrl-0 = <&pinctrl_enet_pwr>;
 141                 compatible = "regulator-fixed";
 142                 regulator-name = "ethernet-supply";
 143                 regulator-min-microvolt = <3300000>;
 144                 regulator-max-microvolt = <3300000>;
 145                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
 146                 startup-delay-us = <70000>;
 147                 enable-active-high;
 148                 vin-supply = <&sw4_reg>;
 149         };
 150
 151         reg_audio: regulator-audio@4 {
 152                 pinctrl-names = "default";
 153                 pinctrl-0 = <&pinctrl_reg_audio>;
 154                 compatible = "regulator-fixed";
 155                 regulator-name = "3v3_aud";
 156                 regulator-min-microvolt = <3300000>;
 157                 regulator-max-microvolt = <3300000>;
 158                 gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 159                 enable-active-high;
 160                 regulator-always-on;
 161                 vin-supply = <&reg_3v3>;
 162         };
 163
 164         reg_hdmi: regulator-hdmi@5 {
 165                 pinctrl-names = "default";
 166                 pinctrl-0 = <&pinctrl_reg_hdmi>;
 167                 compatible = "regulator-fixed";
 168                 regulator-name = "hdmi-supply";
 169                 regulator-min-microvolt = <3300000>;
 170                 regulator-max-microvolt = <3300000>;
 171                 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 172                 enable-active-high;
 173                 vin-supply = <&reg_3v3>;
 174         };
 175
 176         reg_uart3: regulator-uart3@6 {
 177                 pinctrl-names = "default";
 178                 pinctrl-0 = <&pinctrl_reg_uart3>;
 179                 compatible = "regulator-fixed";
 180                 regulator-name = "uart3-supply";
 181                 gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
 182                 enable-active-high;
 183                 regulator-always-on;
 184                 vin-supply = <&reg_3v3>;
 185         };
 186
 187         reg_1v8: regulator-1v8@7 {
 188                 pinctrl-names = "default";
 189                 pinctrl-0 = <&pinctrl_reg_1v8>;
 190                 compatible = "regulator-fixed";
 191                 regulator-name = "1v8-supply";
 192                 gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
 193                 enable-active-high;
 194                 regulator-always-on;
 195                 vin-supply = <&reg_3v3>;
 196         };
 197
 198         reg_pcie: regulator@8 {
 199                 compatible = "regulator-fixed";
 200                 pinctrl-names = "default";
 201                 pinctrl-0 = <&pinctrl_pcie_reg>;
 202                 regulator-name = "MPCIE_3V3";
 203                 regulator-min-microvolt = <3300000>;
 204                 regulator-max-microvolt = <3300000>;
 205                 gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 206                 enable-active-high;
 207         };
 208
 209         mipi_pwr: regulator@9 {
 210                 compatible = "regulator-fixed";
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&pinctrl_mipi_pwr>;
 213                 regulator-name = "mipi_pwr_en";
 214                 regulator-min-microvolt = <2800000>;
 215                 regulator-max-microvolt = <2800000>;
 216                 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
 217                 enable-active-high;
 218         };
 219
 220         sound {
 221                 compatible = "fsl,imx-audio-wm8962";
 222                 model = "wm8962-audio";
 223                 ssi-controller = <&ssi2>;
 224                 audio-codec = <&codec>;
 225                 audio-routing =
 226                         "Headphone Jack", "HPOUTL",
 227                         "Headphone Jack", "HPOUTR",
 228                         "Ext Spk", "SPKOUTL",
 229                         "Ext Spk", "SPKOUTR",
 230                         "AMIC", "MICBIAS",
 231                         "IN3R", "AMIC";
 232                 mux-int-port = <2>;
 233                 mux-ext-port = <4>;
 234         };
 235 };
 236
 237 &audmux {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&pinctrl_audmux>;
 240         status = "okay";
 241 };
 242
 243 &ecspi1 {
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pinctrl_ecspi1>;
 246         status = "disabled";
 247 };
 248
 249 &pwm3 {
 250         pinctrl-names = "default";
 251         pinctrl-0 = <&pinctrl_pwm3>;
 252 };
 253
 254 &uart3 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_uart3>;
 257         status = "okay";
 258 };
 259
 260 &usbh1 {
 261         vbus-supply = <&reg_usb_h1_vbus>;
 262         status = "okay";
 263 };
 264
 265 &usbotg {
 266         vbus-supply = <&reg_usb_otg_vbus>;
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&pinctrl_usbotg>;
 269         disable-over-current;
 270         status = "okay";
 271 };
 272
 273 &fec {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_enet>;
 276         phy-mode = "rgmii";
 277         phy-reset-duration = <10>;
 278         phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
 279         phy-supply = <&reg_enet>;
 280         interrupt-parent = <&gpio1>;
 281         interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 282         status = "okay";
 283 };
 284
 285 &usdhc2 {
 286         pinctrl-names = "default";
 287         pinctrl-0 = <&pinctrl_usdhc2>;
 288         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 289         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 290         no-1-8-v;
 291         keep-power-in-suspend;
 292         status = "okay";
 293 };
 294
 295 &i2c1 {
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pinctrl_i2c1>;
 298         clock-frequency = <400000>;
 299         status = "okay";
 300
 301         codec: wm8962@1a {
 302                 compatible = "wlf,wm8962";
 303                 reg = <0x1a>;
 304                 clocks = <&clks IMX6QDL_CLK_CKO>;
 305                 clock-names = "xclk";
 306                 DCVDD-supply = <&reg_audio>;
 307                 DBVDD-supply = <&reg_audio>;
 308                 AVDD-supply = <&reg_audio>;
 309                 CPVDD-supply = <&reg_audio>;
 310                 MICVDD-supply = <&reg_audio>;
 311                 PLLVDD-supply = <&reg_audio>;
 312                 SPKVDD1-supply = <&reg_audio>;
 313                 SPKVDD2-supply = <&reg_audio>;
 314                 gpio-cfg = <
 315                         0x0000 /* 0:Default */
 316                         0x0000 /* 1:Default */
 317                         0x0013 /* 2:FN_DMICCLK */
 318                         0x0000 /* 3:Default */
 319                         0x8014 /* 4:FN_DMICCDAT */
 320                         0x0000 /* 5:Default */
 321                 >;
 322         };
 323 };
 324
 325 &i2c3 {
 326         ov5640: camera@10 {
 327                 compatible = "ovti,ov5640";
 328                 pinctrl-names = "default";
 329                 pinctrl-0 = <&pinctrl_ov5640>;
 330                 reg = <0x10>;
 331                 clocks = <&clks IMX6QDL_CLK_CKO>;
 332                 clock-names = "xclk";
 333                 DOVDD-supply = <&mipi_pwr>;
 334                 AVDD-supply = <&mipi_pwr>;
 335                 DVDD-supply = <&mipi_pwr>;
 336                 reset-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
 337                 powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
 338
 339                 port {
 340                         ov5640_to_mipi_csi2: endpoint {
 341                                 remote-endpoint = <&mipi_csi2_in>;
 342                                 clock-lanes = <0>;
 343                                 data-lanes = <1 2>;
 344                         };
 345                 };
 346         };
 347
 348         pcf8575: gpio@20 {
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&pinctrl_pcf8574>;
 351                 compatible = "nxp,pcf8575";
 352                 reg = <0x20>;
 353                 interrupt-parent = <&gpio6>;
 354                 interrupts = <31 IRQ_TYPE_EDGE_FALLING>;
 355                 gpio-controller;
 356                 #gpio-cells = <2>;
 357                 interrupt-controller;
 358                 #interrupt-cells = <2>;
 359                 lines-initial-states = <0x0710>;
 360                 wakeup-source;
 361         };
 362 };
 363
 364 &mipi_csi {
 365         status = "okay";
 366
 367         port@0 {
 368                 reg = <0>;
 369
 370                 mipi_csi2_in: endpoint {
 371                         remote-endpoint = <&ov5640_to_mipi_csi2>;
 372                         clock-lanes = <0>;
 373                         data-lanes = <1 2>;
 374                 };
 375         };
 376 };
 377
 378 &pcie {
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_pcie>;
 381         reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
 382         status = "okay";
 383         vpcie-supply = <&reg_pcie>;
 384         /* fsl,max-link-speed = <2>; */
 385 };
 386
 387 &ssi2 {
 388         status = "okay";
 389 };
 390
 391 &iomuxc {
 392
 393         pinctrl_audmux: audmuxgrp {
 394                 fsl,pins = <
 395                         MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
 396                         MX6QDL_PAD_DISP0_DAT21__AUD4_TXD  0x110b0
 397                         MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
 398                         MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
 399                 >;
 400         };
 401
 402         pinctrl_i2c1: i2c1 {
 403                 fsl,pins = <
 404                         MX6QDL_PAD_EIM_D21__I2C1_SCL    0x4001b8b1
 405                         MX6QDL_PAD_EIM_D28__I2C1_SDA    0x4001b8b1
 406                 >;
 407         };
 408
 409         pinctrl_enet_pwr: enet_pwr {
 410                 fsl,pins = <
 411                         MX6QDL_PAD_EIM_D31__GPIO3_IO31  0x1b0b0
 412                 >;
 413         };
 414
 415         pinctrl_mipi_pwr: pwr_mipi {
 416                 fsl,pins = <MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b1>;
 417         };
 418
 419         pinctrl_ov5640: ov5640grp {
 420                 fsl,pins = <
 421                         MX6QDL_PAD_EIM_D26__GPIO3_IO26  0x1b0b1
 422                         MX6QDL_PAD_EIM_D27__GPIO3_IO27  0x1b0b1
 423                 >;
 424         };
 425
 426         pinctrl_reg_hdmi: reg_hdmi {
 427                 fsl,pins = <
 428                         MX6QDL_PAD_EIM_D20__GPIO3_IO20  0x1b0b0
 429                 >;
 430         };
 431
 432         pinctrl_uart3: uart3grp {
 433                 fsl,pins = <
 434                         MX6QDL_PAD_EIM_D23__UART3_CTS_B         0x1b0b1
 435                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 436                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 437                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B         0x1b0b1
 438                 >;
 439         };
 440
 441         pinctrl_usbotg: usbotggrp {
 442                 fsl,pins = <
 443                         MX6QDL_PAD_GPIO_1__USB_OTG_ID   0xd17059
 444                         MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0
 445                 >;
 446         };
 447
 448         pinctrl_ecspi1: ecspi1grp {
 449                 fsl,pins = <
 450                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 451                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 452                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 453                         MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0         0x100b1
 454                 >;
 455         };
 456
 457         pinctrl_usdhc2: usdhc2grp {
 458                 fsl,pins = <
 459                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
 460                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17069
 461                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
 462                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17069
 463                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17069
 464                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17069
 465                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17069
 466                 >;
 467         };
 468
 469         pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
 470                 fsl,pins = <
 471                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
 472                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
 473                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
 474                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
 475                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
 476                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
 477                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
 478                 >;
 479         };
 480
 481         pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
 482                 fsl,pins = <
 483                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1b0b0 /* CD */
 484                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
 485                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
 486                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
 487                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
 488                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
 489                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
 490                 >;
 491         };
 492
 493         pinctrl_enet: enetgrp {
 494                 fsl,pins = <
 495                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b8b0
 496                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 497                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 498                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 499                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 500                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 501                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 502                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 503                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 504                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 505                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 506                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x13030
 507                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x13030
 508                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 509                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 510                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x13030
 511                         MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x1b0b0 /* ENET_INT */
 512                         MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24       0x1b0b0 /* ETHR_nRST */
 513                 >;
 514         };
 515
 516         pinctrl_reg_audio: audio-reg {
 517                 fsl,pins = <
 518                         MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
 519                 >;
 520         };
 521
 522         pinctrl_pcie: pcie {
 523                 fsl,pins = <
 524                         MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
 525                         MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
 526                 >;
 527         };
 528
 529         pinctrl_pcie_reg: pciereggrp {
 530                 fsl,pins = <
 531                         MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x1b0b0
 532                         >;
 533         };
 534
 535         pinctrl_pcf8574: pcf8575-pins {
 536                 fsl,pins = <
 537                         MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0
 538                 >;
 539         };
 540
 541         pinctrl_lcd: lcdgrp {
 542                 fsl,pins = <
 543                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* R_LCD_DCLK */
 544                         MX6QDL_PAD_DI0_PIN15__GPIO4_IO17        0x100b0 /* R_LCD_PANEL_PWR */
 545                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02     0x10    /* R_LCD_HSYNC */
 546                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03     0x10    /* R_LCD_VSYNC */
 547                         MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04     0x10    /* R_LCD_MDISP */
 548                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x10
 549                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x10
 550                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
 551                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
 552                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
 553                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
 554                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
 555                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
 556                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
 557                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
 558                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
 559                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
 560                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
 561                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
 562                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
 563                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
 564                 >;
 565         };
 566
 567         pinctrl_pwm3: pwm3grp {
 568                 fsl,pins = <
 569                         MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
 570                 >;
 571         };
 572
 573         pinctrl_reg_uart3: uart3reg {
 574                 fsl,pins = <
 575                         MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x1b0b0
 576                 >;
 577         };
 578
 579         pinctrl_reg_3v3: reg-3v3 {
 580                 fsl,pins = <
 581                         MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b0
 582                 >;
 583         };
 584
 585         pinctrl_reg_1v8: reg-1v8 {
 586                 fsl,pins = <
 587                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x1b0b0
 588                 >;
 589         };
 590
 591         pinctrl_led0: led0 {
 592                 fsl,pins = <
 593                         MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 594                 >;
 595         };
 596 };