5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime"
199 depends on !XIP_KERNEL && MMU
200 depends on !ARCH_REALVIEW || !SPARSEMEM
202 Patch phys-to-virt and virt-to-phys translation functions at
203 boot and module load time according to the position of the
204 kernel in system memory.
206 This can only be used with non-XIP MMU kernels where the base
207 of physical memory is at a 16MB boundary, or theoretically 64K
208 for the MSM machine class.
210 config ARM_PATCH_PHYS_VIRT_16BIT
212 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
214 This option extends the physical to virtual translation patching
215 to allow physical memory down to a theoretical minimum of 64K
218 source "init/Kconfig"
220 source "kernel/Kconfig.freezer"
225 bool "MMU-based Paged Memory Management Support"
228 Select if you want MMU-based virtualised addressing space
229 support by paged memory management. If unsure, say 'Y'.
232 # The "ARM system type" choice list is ordered alphabetically by option
233 # text. Please add new entries in the option alphabetic order.
236 prompt "ARM system type"
237 default ARCH_VERSATILE
239 config ARCH_INTEGRATOR
240 bool "ARM Ltd. Integrator family"
242 select ARCH_HAS_CPUFREQ
244 select HAVE_MACH_CLKDEV
246 select GENERIC_CLOCKEVENTS
247 select PLAT_VERSATILE
248 select PLAT_VERSATILE_FPGA_IRQ
250 Support for ARM's Integrator platform.
253 bool "ARM Ltd. RealView family"
256 select HAVE_MACH_CLKDEV
258 select GENERIC_CLOCKEVENTS
259 select ARCH_WANT_OPTIONAL_GPIOLIB
260 select PLAT_VERSATILE
261 select PLAT_VERSATILE_CLCD
262 select ARM_TIMER_SP804
263 select GPIO_PL061 if GPIOLIB
265 This enables support for ARM Ltd RealView boards.
267 config ARCH_VERSATILE
268 bool "ARM Ltd. Versatile family"
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select PLAT_VERSATILE_FPGA_IRQ
279 select ARM_TIMER_SP804
281 This enables support for ARM Ltd Versatile board.
284 bool "ARM Ltd. Versatile Express family"
285 select ARCH_WANT_OPTIONAL_GPIOLIB
287 select ARM_TIMER_SP804
289 select HAVE_MACH_CLKDEV
290 select GENERIC_CLOCKEVENTS
292 select HAVE_PATA_PLATFORM
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
297 This enables support for the ARM Ltd Versatile Express boards.
301 select ARCH_REQUIRE_GPIOLIB
304 select ARM_PATCH_PHYS_VIRT if MMU
306 This enables support for systems based on the Atmel AT91RM9200,
307 AT91SAM9 and AT91CAP9 processors.
310 bool "Broadcom BCMRING"
314 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select ARCH_WANT_OPTIONAL_GPIOLIB
319 Support for Broadcom's BCMRing platform.
322 bool "Cirrus Logic CLPS711x/EP721x-based"
324 select ARCH_USES_GETTIMEOFFSET
326 Support for Cirrus Logic 711x/721x based boards.
329 bool "Cavium Networks CNS3XXX family"
331 select GENERIC_CLOCKEVENTS
333 select MIGHT_HAVE_PCI
334 select PCI_DOMAINS if PCI
336 Support for Cavium Networks CNS3XXX platform.
339 bool "Cortina Systems Gemini"
341 select ARCH_REQUIRE_GPIOLIB
342 select ARCH_USES_GETTIMEOFFSET
344 Support for the Cortina Systems Gemini family SoCs
347 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
351 select GENERIC_CLOCKEVENTS
353 select GENERIC_IRQ_CHIP
357 Support for CSR SiRFSoC ARM Cortex A9 Platform
364 select ARCH_USES_GETTIMEOFFSET
366 This is an evaluation board for the StrongARM processor available
367 from Digital. It has limited hardware on-board, including an
368 Ethernet interface, two PCMCIA sockets, two serial ports and a
377 select ARCH_REQUIRE_GPIOLIB
378 select ARCH_HAS_HOLES_MEMORYMODEL
379 select ARCH_USES_GETTIMEOFFSET
381 This enables support for the Cirrus EP93xx series of CPUs.
383 config ARCH_FOOTBRIDGE
387 select GENERIC_CLOCKEVENTS
390 Support for systems based on the DC21285 companion chip
391 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
394 bool "Freescale MXC/iMX-based"
395 select GENERIC_CLOCKEVENTS
396 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_IRQ_CHIP
400 select HAVE_SCHED_CLOCK
402 Support for Freescale MXC/iMX-based family of processors
405 bool "Freescale MXS-based"
406 select GENERIC_CLOCKEVENTS
407 select ARCH_REQUIRE_GPIOLIB
411 Support for Freescale MXS-based family of processors
414 bool "Hilscher NetX based"
418 select GENERIC_CLOCKEVENTS
420 This enables support for systems based on the Hilscher NetX Soc
423 bool "Hynix HMS720x-based"
426 select ARCH_USES_GETTIMEOFFSET
428 This enables support for systems based on the Hynix HMS720x
436 select ARCH_SUPPORTS_MSI
439 Support for Intel's IOP13XX (XScale) family of processors.
447 select ARCH_REQUIRE_GPIOLIB
449 Support for Intel's 80219 and IOP32X (XScale) family of
458 select ARCH_REQUIRE_GPIOLIB
460 Support for Intel's IOP33X (XScale) family of processors.
467 select ARCH_USES_GETTIMEOFFSET
469 Support for Intel's IXP23xx (XScale) family of processors.
472 bool "IXP2400/2800-based"
476 select ARCH_USES_GETTIMEOFFSET
478 Support for Intel's IXP2400/2800 (XScale) family of processors.
486 select GENERIC_CLOCKEVENTS
487 select HAVE_SCHED_CLOCK
488 select MIGHT_HAVE_PCI
489 select DMABOUNCE if PCI
491 Support for Intel's IXP4XX (XScale) family of processors.
497 select ARCH_REQUIRE_GPIOLIB
498 select GENERIC_CLOCKEVENTS
501 Support for the Marvell Dove SoC 88AP510
504 bool "Marvell Kirkwood"
507 select ARCH_REQUIRE_GPIOLIB
508 select GENERIC_CLOCKEVENTS
511 Support for the following Marvell Kirkwood series SoCs:
512 88F6180, 88F6192 and 88F6281.
518 select ARCH_REQUIRE_GPIOLIB
521 select USB_ARCH_HAS_OHCI
524 select GENERIC_CLOCKEVENTS
526 Support for the NXP LPC32XX family of processors
529 bool "Marvell MV78xx0"
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 Support for the following Marvell MV78xx0 series SoCs:
544 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
548 Support for the following Marvell Orion 5x series SoCs:
549 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
550 Orion-2 (5281), Orion-1-90 (6183).
553 bool "Marvell PXA168/910/MMP2"
555 select ARCH_REQUIRE_GPIOLIB
557 select GENERIC_CLOCKEVENTS
558 select HAVE_SCHED_CLOCK
563 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
566 bool "Micrel/Kendin KS8695"
568 select ARCH_REQUIRE_GPIOLIB
569 select ARCH_USES_GETTIMEOFFSET
571 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
572 System-on-Chip devices.
575 bool "Nuvoton W90X900 CPU"
577 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
582 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
583 At present, the w90x900 has been renamed nuc900, regarding
584 the ARM series product line, you can login the following
585 link address to know more.
587 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
588 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
591 bool "Nuvoton NUC93X CPU"
595 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
596 low-power and high performance MPEG-4/JPEG multimedia controller chip.
603 select GENERIC_CLOCKEVENTS
606 select HAVE_SCHED_CLOCK
607 select ARCH_HAS_CPUFREQ
609 This enables support for NVIDIA Tegra based systems (Tegra APX,
610 Tegra 6xx and Tegra 2 series).
613 bool "Philips Nexperia PNX4008 Mobile"
616 select ARCH_USES_GETTIMEOFFSET
618 This enables support for Philips PNX4008 mobile platform.
621 bool "PXA2xx/PXA3xx-based"
624 select ARCH_HAS_CPUFREQ
627 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
629 select HAVE_SCHED_CLOCK
634 select MULTI_IRQ_HANDLER
635 select ARM_CPU_SUSPEND if PM
638 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
643 select GENERIC_CLOCKEVENTS
644 select ARCH_REQUIRE_GPIOLIB
647 Support for Qualcomm MSM/QSD based systems. This runs on the
648 apps processor of the MSM/QSD and depends on a shared memory
649 interface to the modem processor which runs the baseband
650 stack and controls some vital subsystems
651 (clock and power control, etc).
654 bool "Renesas SH-Mobile / R-Mobile"
657 select HAVE_MACH_CLKDEV
658 select GENERIC_CLOCKEVENTS
661 select MULTI_IRQ_HANDLER
662 select PM_GENERIC_DOMAINS if PM
664 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
671 select ARCH_MAY_HAVE_PC_FDC
672 select HAVE_PATA_PLATFORM
675 select ARCH_SPARSEMEM_ENABLE
676 select ARCH_USES_GETTIMEOFFSET
679 On the Acorn Risc-PC, Linux can support the internal IDE disk and
680 CD-ROM interface, serial and parallel port, and the floppy drive.
687 select ARCH_SPARSEMEM_ENABLE
689 select ARCH_HAS_CPUFREQ
691 select GENERIC_CLOCKEVENTS
693 select HAVE_SCHED_CLOCK
695 select ARCH_REQUIRE_GPIOLIB
698 Support for StrongARM 11x0 based boards.
701 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
703 select ARCH_HAS_CPUFREQ
706 select ARCH_USES_GETTIMEOFFSET
707 select HAVE_S3C2410_I2C if I2C
709 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
710 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
711 the Samsung SMDK2410 development board (and derivatives).
713 Note, the S3C2416 and the S3C2450 are so close that they even share
714 the same SoC ID code. This means that there is no separate machine
715 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
718 bool "Samsung S3C64XX"
725 select ARCH_USES_GETTIMEOFFSET
726 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
728 select SAMSUNG_CLKSRC
729 select SAMSUNG_IRQ_VIC_TIMER
730 select SAMSUNG_IRQ_UART
731 select S3C_GPIO_TRACK
732 select S3C_GPIO_PULL_UPDOWN
733 select S3C_GPIO_CFG_S3C24XX
734 select S3C_GPIO_CFG_S3C64XX
736 select USB_ARCH_HAS_OHCI
737 select SAMSUNG_GPIOLIB_4BIT
738 select HAVE_S3C2410_I2C if I2C
739 select HAVE_S3C2410_WATCHDOG if WATCHDOG
741 Samsung S3C64XX series based systems
744 bool "Samsung S5P6440 S5P6450"
750 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select GENERIC_CLOCKEVENTS
752 select HAVE_SCHED_CLOCK
753 select HAVE_S3C2410_I2C if I2C
754 select HAVE_S3C_RTC if RTC_CLASS
756 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
760 bool "Samsung S5PC100"
765 select ARM_L1_CACHE_SHIFT_6
766 select ARCH_USES_GETTIMEOFFSET
767 select HAVE_S3C2410_I2C if I2C
768 select HAVE_S3C_RTC if RTC_CLASS
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 Samsung S5PC100 series based systems
774 bool "Samsung S5PV210/S5PC110"
776 select ARCH_SPARSEMEM_ENABLE
777 select ARCH_HAS_HOLES_MEMORYMODEL
782 select ARM_L1_CACHE_SHIFT_6
783 select ARCH_HAS_CPUFREQ
784 select GENERIC_CLOCKEVENTS
785 select HAVE_SCHED_CLOCK
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C_RTC if RTC_CLASS
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 Samsung S5PV210/S5PC110 series based systems
793 bool "Samsung EXYNOS4"
795 select ARCH_SPARSEMEM_ENABLE
796 select ARCH_HAS_HOLES_MEMORYMODEL
800 select ARCH_HAS_CPUFREQ
801 select GENERIC_CLOCKEVENTS
802 select HAVE_S3C_RTC if RTC_CLASS
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 Samsung EXYNOS4 series based systems
815 select ARCH_USES_GETTIMEOFFSET
817 Support for the StrongARM based Digital DNARD machine, also known
818 as "Shark" (<http://www.shark-linux.de/shark.html>).
821 bool "Telechips TCC ARM926-based systems"
826 select GENERIC_CLOCKEVENTS
828 Support for Telechips TCC ARM926-based systems.
831 bool "ST-Ericsson U300 Series"
835 select HAVE_SCHED_CLOCK
839 select GENERIC_CLOCKEVENTS
841 select HAVE_MACH_CLKDEV
844 Support for ST-Ericsson U300 series mobile platforms.
847 bool "ST-Ericsson U8500 Series"
850 select GENERIC_CLOCKEVENTS
852 select ARCH_REQUIRE_GPIOLIB
853 select ARCH_HAS_CPUFREQ
855 Support for ST-Ericsson's Ux500 architecture
858 bool "STMicroelectronics Nomadik"
863 select GENERIC_CLOCKEVENTS
864 select ARCH_REQUIRE_GPIOLIB
866 Support for the Nomadik platform by ST-Ericsson
870 select GENERIC_CLOCKEVENTS
871 select ARCH_REQUIRE_GPIOLIB
875 select GENERIC_ALLOCATOR
876 select GENERIC_IRQ_CHIP
877 select ARCH_HAS_HOLES_MEMORYMODEL
879 Support for TI's DaVinci platform.
884 select ARCH_REQUIRE_GPIOLIB
885 select ARCH_HAS_CPUFREQ
887 select GENERIC_CLOCKEVENTS
888 select HAVE_SCHED_CLOCK
889 select ARCH_HAS_HOLES_MEMORYMODEL
891 Support for TI's OMAP platform (OMAP1/2/3/4).
896 select ARCH_REQUIRE_GPIOLIB
899 select GENERIC_CLOCKEVENTS
902 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
905 bool "VIA/WonderMedia 85xx"
908 select ARCH_HAS_CPUFREQ
909 select GENERIC_CLOCKEVENTS
910 select ARCH_REQUIRE_GPIOLIB
913 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
916 bool "Xilinx Zynq ARM Cortex A9 Platform"
919 select GENERIC_CLOCKEVENTS
926 Support for Xilinx Zynq ARM Cortex A9 Platform
930 # This is sorted alphabetically by mach-* pathname. However, plat-*
931 # Kconfigs may be included either alphabetically (according to the
932 # plat- suffix) or along side the corresponding mach-* source.
934 source "arch/arm/mach-at91/Kconfig"
936 source "arch/arm/mach-bcmring/Kconfig"
938 source "arch/arm/mach-clps711x/Kconfig"
940 source "arch/arm/mach-cns3xxx/Kconfig"
942 source "arch/arm/mach-davinci/Kconfig"
944 source "arch/arm/mach-dove/Kconfig"
946 source "arch/arm/mach-ep93xx/Kconfig"
948 source "arch/arm/mach-footbridge/Kconfig"
950 source "arch/arm/mach-gemini/Kconfig"
952 source "arch/arm/mach-h720x/Kconfig"
954 source "arch/arm/mach-integrator/Kconfig"
956 source "arch/arm/mach-iop32x/Kconfig"
958 source "arch/arm/mach-iop33x/Kconfig"
960 source "arch/arm/mach-iop13xx/Kconfig"
962 source "arch/arm/mach-ixp4xx/Kconfig"
964 source "arch/arm/mach-ixp2000/Kconfig"
966 source "arch/arm/mach-ixp23xx/Kconfig"
968 source "arch/arm/mach-kirkwood/Kconfig"
970 source "arch/arm/mach-ks8695/Kconfig"
972 source "arch/arm/mach-lpc32xx/Kconfig"
974 source "arch/arm/mach-msm/Kconfig"
976 source "arch/arm/mach-mv78xx0/Kconfig"
978 source "arch/arm/plat-mxc/Kconfig"
980 source "arch/arm/mach-mxs/Kconfig"
982 source "arch/arm/mach-netx/Kconfig"
984 source "arch/arm/mach-nomadik/Kconfig"
985 source "arch/arm/plat-nomadik/Kconfig"
987 source "arch/arm/mach-nuc93x/Kconfig"
989 source "arch/arm/plat-omap/Kconfig"
991 source "arch/arm/mach-omap1/Kconfig"
993 source "arch/arm/mach-omap2/Kconfig"
995 source "arch/arm/mach-orion5x/Kconfig"
997 source "arch/arm/mach-pxa/Kconfig"
998 source "arch/arm/plat-pxa/Kconfig"
1000 source "arch/arm/mach-mmp/Kconfig"
1002 source "arch/arm/mach-realview/Kconfig"
1004 source "arch/arm/mach-sa1100/Kconfig"
1006 source "arch/arm/plat-samsung/Kconfig"
1007 source "arch/arm/plat-s3c24xx/Kconfig"
1008 source "arch/arm/plat-s5p/Kconfig"
1010 source "arch/arm/plat-spear/Kconfig"
1012 source "arch/arm/plat-tcc/Kconfig"
1015 source "arch/arm/mach-s3c2410/Kconfig"
1016 source "arch/arm/mach-s3c2412/Kconfig"
1017 source "arch/arm/mach-s3c2416/Kconfig"
1018 source "arch/arm/mach-s3c2440/Kconfig"
1019 source "arch/arm/mach-s3c2443/Kconfig"
1023 source "arch/arm/mach-s3c64xx/Kconfig"
1026 source "arch/arm/mach-s5p64x0/Kconfig"
1028 source "arch/arm/mach-s5pc100/Kconfig"
1030 source "arch/arm/mach-s5pv210/Kconfig"
1032 source "arch/arm/mach-exynos4/Kconfig"
1034 source "arch/arm/mach-shmobile/Kconfig"
1036 source "arch/arm/mach-tegra/Kconfig"
1038 source "arch/arm/mach-u300/Kconfig"
1040 source "arch/arm/mach-ux500/Kconfig"
1042 source "arch/arm/mach-versatile/Kconfig"
1044 source "arch/arm/mach-vexpress/Kconfig"
1045 source "arch/arm/plat-versatile/Kconfig"
1047 source "arch/arm/mach-vt8500/Kconfig"
1049 source "arch/arm/mach-w90x900/Kconfig"
1051 # Definitions to make life easier
1057 select GENERIC_CLOCKEVENTS
1058 select HAVE_SCHED_CLOCK
1063 select GENERIC_IRQ_CHIP
1064 select HAVE_SCHED_CLOCK
1069 config PLAT_VERSATILE
1072 config ARM_TIMER_SP804
1076 source arch/arm/mm/Kconfig
1079 bool "Enable iWMMXt support"
1080 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1081 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1083 Enable support for iWMMXt context switching at run time if
1084 running on a CPU that supports it.
1086 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1089 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1093 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1094 (!ARCH_OMAP3 || OMAP3_EMU)
1098 config MULTI_IRQ_HANDLER
1101 Allow each machine to specify it's own IRQ handler at run time.
1104 source "arch/arm/Kconfig-nommu"
1107 config ARM_ERRATA_411920
1108 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1109 depends on CPU_V6 || CPU_V6K
1111 Invalidation of the Instruction Cache operation can
1112 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1113 It does not affect the MPCore. This option enables the ARM Ltd.
1114 recommended workaround.
1116 config ARM_ERRATA_430973
1117 bool "ARM errata: Stale prediction on replaced interworking branch"
1120 This option enables the workaround for the 430973 Cortex-A8
1121 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1122 interworking branch is replaced with another code sequence at the
1123 same virtual address, whether due to self-modifying code or virtual
1124 to physical address re-mapping, Cortex-A8 does not recover from the
1125 stale interworking branch prediction. This results in Cortex-A8
1126 executing the new code sequence in the incorrect ARM or Thumb state.
1127 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1128 and also flushes the branch target cache at every context switch.
1129 Note that setting specific bits in the ACTLR register may not be
1130 available in non-secure mode.
1132 config ARM_ERRATA_458693
1133 bool "ARM errata: Processor deadlock when a false hazard is created"
1136 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1137 erratum. For very specific sequences of memory operations, it is
1138 possible for a hazard condition intended for a cache line to instead
1139 be incorrectly associated with a different cache line. This false
1140 hazard might then cause a processor deadlock. The workaround enables
1141 the L1 caching of the NEON accesses and disables the PLD instruction
1142 in the ACTLR register. Note that setting specific bits in the ACTLR
1143 register may not be available in non-secure mode.
1145 config ARM_ERRATA_460075
1146 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1149 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1150 erratum. Any asynchronous access to the L2 cache may encounter a
1151 situation in which recent store transactions to the L2 cache are lost
1152 and overwritten with stale memory contents from external memory. The
1153 workaround disables the write-allocate mode for the L2 cache via the
1154 ACTLR register. Note that setting specific bits in the ACTLR register
1155 may not be available in non-secure mode.
1157 config ARM_ERRATA_742230
1158 bool "ARM errata: DMB operation may be faulty"
1159 depends on CPU_V7 && SMP
1161 This option enables the workaround for the 742230 Cortex-A9
1162 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1163 between two write operations may not ensure the correct visibility
1164 ordering of the two writes. This workaround sets a specific bit in
1165 the diagnostic register of the Cortex-A9 which causes the DMB
1166 instruction to behave as a DSB, ensuring the correct behaviour of
1169 config ARM_ERRATA_742231
1170 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1171 depends on CPU_V7 && SMP
1173 This option enables the workaround for the 742231 Cortex-A9
1174 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1175 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1176 accessing some data located in the same cache line, may get corrupted
1177 data due to bad handling of the address hazard when the line gets
1178 replaced from one of the CPUs at the same time as another CPU is
1179 accessing it. This workaround sets specific bits in the diagnostic
1180 register of the Cortex-A9 which reduces the linefill issuing
1181 capabilities of the processor.
1183 config PL310_ERRATA_588369
1184 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1185 depends on CACHE_L2X0
1187 The PL310 L2 cache controller implements three types of Clean &
1188 Invalidate maintenance operations: by Physical Address
1189 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1190 They are architecturally defined to behave as the execution of a
1191 clean operation followed immediately by an invalidate operation,
1192 both performing to the same memory location. This functionality
1193 is not correctly implemented in PL310 as clean lines are not
1194 invalidated as a result of these operations.
1196 config ARM_ERRATA_720789
1197 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1198 depends on CPU_V7 && SMP
1200 This option enables the workaround for the 720789 Cortex-A9 (prior to
1201 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1202 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1203 As a consequence of this erratum, some TLB entries which should be
1204 invalidated are not, resulting in an incoherency in the system page
1205 tables. The workaround changes the TLB flushing routines to invalidate
1206 entries regardless of the ASID.
1208 config PL310_ERRATA_727915
1209 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1210 depends on CACHE_L2X0
1212 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1213 operation (offset 0x7FC). This operation runs in background so that
1214 PL310 can handle normal accesses while it is in progress. Under very
1215 rare circumstances, due to this erratum, write data can be lost when
1216 PL310 treats a cacheable write transaction during a Clean &
1217 Invalidate by Way operation.
1219 config ARM_ERRATA_743622
1220 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1223 This option enables the workaround for the 743622 Cortex-A9
1224 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1225 optimisation in the Cortex-A9 Store Buffer may lead to data
1226 corruption. This workaround sets a specific bit in the diagnostic
1227 register of the Cortex-A9 which disables the Store Buffer
1228 optimisation, preventing the defect from occurring. This has no
1229 visible impact on the overall performance or power consumption of the
1232 config ARM_ERRATA_751472
1233 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1234 depends on CPU_V7 && SMP
1236 This option enables the workaround for the 751472 Cortex-A9 (prior
1237 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1238 completion of a following broadcasted operation if the second
1239 operation is received by a CPU before the ICIALLUIS has completed,
1240 potentially leading to corrupted entries in the cache or TLB.
1242 config ARM_ERRATA_753970
1243 bool "ARM errata: cache sync operation may be faulty"
1244 depends on CACHE_PL310
1246 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1248 Under some condition the effect of cache sync operation on
1249 the store buffer still remains when the operation completes.
1250 This means that the store buffer is always asked to drain and
1251 this prevents it from merging any further writes. The workaround
1252 is to replace the normal offset of cache sync operation (0x730)
1253 by another offset targeting an unmapped PL310 register 0x740.
1254 This has the same effect as the cache sync operation: store buffer
1255 drain and waiting for all buffers empty.
1257 config ARM_ERRATA_754322
1258 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1261 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1262 r3p*) erratum. A speculative memory access may cause a page table walk
1263 which starts prior to an ASID switch but completes afterwards. This
1264 can populate the micro-TLB with a stale entry which may be hit with
1265 the new ASID. This workaround places two dsb instructions in the mm
1266 switching code so that no page table walks can cross the ASID switch.
1268 config ARM_ERRATA_754327
1269 bool "ARM errata: no automatic Store Buffer drain"
1270 depends on CPU_V7 && SMP
1272 This option enables the workaround for the 754327 Cortex-A9 (prior to
1273 r2p0) erratum. The Store Buffer does not have any automatic draining
1274 mechanism and therefore a livelock may occur if an external agent
1275 continuously polls a memory location waiting to observe an update.
1276 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1277 written polling loops from denying visibility of updates to memory.
1281 source "arch/arm/common/Kconfig"
1291 Find out whether you have ISA slots on your motherboard. ISA is the
1292 name of a bus system, i.e. the way the CPU talks to the other stuff
1293 inside your box. Other bus systems are PCI, EISA, MicroChannel
1294 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1295 newer boards don't support it. If you have ISA, say Y, otherwise N.
1297 # Select ISA DMA controller support
1302 # Select ISA DMA interface
1307 bool "PCI support" if MIGHT_HAVE_PCI
1309 Find out whether you have a PCI motherboard. PCI is the name of a
1310 bus system, i.e. the way the CPU talks to the other stuff inside
1311 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1312 VESA. If you have PCI, say Y, otherwise N.
1318 config PCI_NANOENGINE
1319 bool "BSE nanoEngine PCI support"
1320 depends on SA1100_NANOENGINE
1322 Enable PCI on the BSE nanoEngine board.
1327 # Select the host bridge type
1328 config PCI_HOST_VIA82C505
1330 depends on PCI && ARCH_SHARK
1333 config PCI_HOST_ITE8152
1335 depends on PCI && MACH_ARMCORE
1339 source "drivers/pci/Kconfig"
1341 source "drivers/pcmcia/Kconfig"
1345 menu "Kernel Features"
1347 source "kernel/time/Kconfig"
1350 bool "Symmetric Multi-Processing"
1351 depends on CPU_V6K || CPU_V7
1352 depends on GENERIC_CLOCKEVENTS
1353 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1354 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1355 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1356 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1358 select USE_GENERIC_SMP_HELPERS
1359 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1361 This enables support for systems with more than one CPU. If you have
1362 a system with only one CPU, like most personal computers, say N. If
1363 you have a system with more than one CPU, say Y.
1365 If you say N here, the kernel will run on single and multiprocessor
1366 machines, but will use only one CPU of a multiprocessor machine. If
1367 you say Y here, the kernel will run on many, but not all, single
1368 processor machines. On a single processor machine, the kernel will
1369 run faster if you say N here.
1371 See also <file:Documentation/i386/IO-APIC.txt>,
1372 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1373 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1375 If you don't know what to do here, say N.
1378 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1379 depends on EXPERIMENTAL
1380 depends on SMP && !XIP_KERNEL
1383 SMP kernels contain instructions which fail on non-SMP processors.
1384 Enabling this option allows the kernel to modify itself to make
1385 these instructions safe. Disabling it allows about 1K of space
1388 If you don't know what to do here, say Y.
1393 This option enables support for the ARM system coherency unit
1400 This options enables support for the ARM timer and watchdog unit
1403 prompt "Memory split"
1406 Select the desired split between kernel and user memory.
1408 If you are not absolutely sure what you are doing, leave this
1412 bool "3G/1G user/kernel split"
1414 bool "2G/2G user/kernel split"
1416 bool "1G/3G user/kernel split"
1421 default 0x40000000 if VMSPLIT_1G
1422 default 0x80000000 if VMSPLIT_2G
1426 int "Maximum number of CPUs (2-32)"
1432 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1433 depends on SMP && HOTPLUG && EXPERIMENTAL
1435 Say Y here to experiment with turning CPUs off and on. CPUs
1436 can be controlled through /sys/devices/system/cpu.
1439 bool "Use local timer interrupts"
1442 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1444 Enable support for local timers on SMP platforms, rather then the
1445 legacy IPI broadcast method. Local timers allows the system
1446 accounting to be spread across the timer interval, preventing a
1447 "thundering herd" at every timer tick.
1449 source kernel/Kconfig.preempt
1453 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1454 ARCH_S5PV210 || ARCH_EXYNOS4
1455 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1456 default AT91_TIMER_HZ if ARCH_AT91
1457 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1460 config THUMB2_KERNEL
1461 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1462 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1464 select ARM_ASM_UNIFIED
1467 By enabling this option, the kernel will be compiled in
1468 Thumb-2 mode. A compiler/assembler that understand the unified
1469 ARM-Thumb syntax is needed.
1473 config THUMB2_AVOID_R_ARM_THM_JUMP11
1474 bool "Work around buggy Thumb-2 short branch relocations in gas"
1475 depends on THUMB2_KERNEL && MODULES
1478 Various binutils versions can resolve Thumb-2 branches to
1479 locally-defined, preemptible global symbols as short-range "b.n"
1480 branch instructions.
1482 This is a problem, because there's no guarantee the final
1483 destination of the symbol, or any candidate locations for a
1484 trampoline, are within range of the branch. For this reason, the
1485 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1486 relocation in modules at all, and it makes little sense to add
1489 The symptom is that the kernel fails with an "unsupported
1490 relocation" error when loading some modules.
1492 Until fixed tools are available, passing
1493 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1494 code which hits this problem, at the cost of a bit of extra runtime
1495 stack usage in some cases.
1497 The problem is described in more detail at:
1498 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1500 Only Thumb-2 kernels are affected.
1502 Unless you are sure your tools don't have this problem, say Y.
1504 config ARM_ASM_UNIFIED
1508 bool "Use the ARM EABI to compile the kernel"
1510 This option allows for the kernel to be compiled using the latest
1511 ARM ABI (aka EABI). This is only useful if you are using a user
1512 space environment that is also compiled with EABI.
1514 Since there are major incompatibilities between the legacy ABI and
1515 EABI, especially with regard to structure member alignment, this
1516 option also changes the kernel syscall calling convention to
1517 disambiguate both ABIs and allow for backward compatibility support
1518 (selected with CONFIG_OABI_COMPAT).
1520 To use this you need GCC version 4.0.0 or later.
1523 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1524 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1527 This option preserves the old syscall interface along with the
1528 new (ARM EABI) one. It also provides a compatibility layer to
1529 intercept syscalls that have structure arguments which layout
1530 in memory differs between the legacy ABI and the new ARM EABI
1531 (only for non "thumb" binaries). This option adds a tiny
1532 overhead to all syscalls and produces a slightly larger kernel.
1533 If you know you'll be using only pure EABI user space then you
1534 can say N here. If this option is not selected and you attempt
1535 to execute a legacy ABI binary then the result will be
1536 UNPREDICTABLE (in fact it can be predicted that it won't work
1537 at all). If in doubt say Y.
1539 config ARCH_HAS_HOLES_MEMORYMODEL
1542 config ARCH_SPARSEMEM_ENABLE
1545 config ARCH_SPARSEMEM_DEFAULT
1546 def_bool ARCH_SPARSEMEM_ENABLE
1548 config ARCH_SELECT_MEMORY_MODEL
1549 def_bool ARCH_SPARSEMEM_ENABLE
1551 config HAVE_ARCH_PFN_VALID
1552 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1555 bool "High Memory Support"
1558 The address space of ARM processors is only 4 Gigabytes large
1559 and it has to accommodate user address space, kernel address
1560 space as well as some memory mapped IO. That means that, if you
1561 have a large amount of physical memory and/or IO, not all of the
1562 memory can be "permanently mapped" by the kernel. The physical
1563 memory that is not permanently mapped is called "high memory".
1565 Depending on the selected kernel/user memory split, minimum
1566 vmalloc space and actual amount of RAM, you may not need this
1567 option which should result in a slightly faster kernel.
1572 bool "Allocate 2nd-level pagetables from highmem"
1575 config HW_PERF_EVENTS
1576 bool "Enable hardware performance counter support for perf events"
1577 depends on PERF_EVENTS && CPU_HAS_PMU
1580 Enable hardware performance counter support for perf events. If
1581 disabled, perf events will use software events only.
1585 config FORCE_MAX_ZONEORDER
1586 int "Maximum zone order" if ARCH_SHMOBILE
1587 range 11 64 if ARCH_SHMOBILE
1588 default "9" if SA1111
1591 The kernel memory allocator divides physically contiguous memory
1592 blocks into "zones", where each zone is a power of two number of
1593 pages. This option selects the largest power of two that the kernel
1594 keeps in the memory allocator. If you need to allocate very large
1595 blocks of physically contiguous memory, then you may need to
1596 increase this value.
1598 This config option is actually maximum order plus one. For example,
1599 a value of 11 means that the largest free memory block is 2^10 pages.
1602 bool "Timer and CPU usage LEDs"
1603 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1604 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1605 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1606 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1607 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1608 ARCH_AT91 || ARCH_DAVINCI || \
1609 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1611 If you say Y here, the LEDs on your machine will be used
1612 to provide useful information about your current system status.
1614 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1615 be able to select which LEDs are active using the options below. If
1616 you are compiling a kernel for the EBSA-110 or the LART however, the
1617 red LED will simply flash regularly to indicate that the system is
1618 still functional. It is safe to say Y here if you have a CATS
1619 system, but the driver will do nothing.
1622 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1623 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1624 || MACH_OMAP_PERSEUS2
1626 depends on !GENERIC_CLOCKEVENTS
1627 default y if ARCH_EBSA110
1629 If you say Y here, one of the system LEDs (the green one on the
1630 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1631 will flash regularly to indicate that the system is still
1632 operational. This is mainly useful to kernel hackers who are
1633 debugging unstable kernels.
1635 The LART uses the same LED for both Timer LED and CPU usage LED
1636 functions. You may choose to use both, but the Timer LED function
1637 will overrule the CPU usage LED.
1640 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1642 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1643 || MACH_OMAP_PERSEUS2
1646 If you say Y here, the red LED will be used to give a good real
1647 time indication of CPU usage, by lighting whenever the idle task
1648 is not currently executing.
1650 The LART uses the same LED for both Timer LED and CPU usage LED
1651 functions. You may choose to use both, but the Timer LED function
1652 will overrule the CPU usage LED.
1654 config ALIGNMENT_TRAP
1656 depends on CPU_CP15_MMU
1657 default y if !ARCH_EBSA110
1658 select HAVE_PROC_CPU if PROC_FS
1660 ARM processors cannot fetch/store information which is not
1661 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1662 address divisible by 4. On 32-bit ARM processors, these non-aligned
1663 fetch/store instructions will be emulated in software if you say
1664 here, which has a severe performance impact. This is necessary for
1665 correct operation of some network protocols. With an IP-only
1666 configuration it is safe to say N, otherwise say Y.
1668 config UACCESS_WITH_MEMCPY
1669 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1670 depends on MMU && EXPERIMENTAL
1671 default y if CPU_FEROCEON
1673 Implement faster copy_to_user and clear_user methods for CPU
1674 cores where a 8-word STM instruction give significantly higher
1675 memory write throughput than a sequence of individual 32bit stores.
1677 A possible side effect is a slight increase in scheduling latency
1678 between threads sharing the same address space if they invoke
1679 such copy operations with large buffers.
1681 However, if the CPU data cache is using a write-allocate mode,
1682 this option is unlikely to provide any performance gain.
1686 prompt "Enable seccomp to safely compute untrusted bytecode"
1688 This kernel feature is useful for number crunching applications
1689 that may need to compute untrusted bytecode during their
1690 execution. By using pipes or other transports made available to
1691 the process as file descriptors supporting the read/write
1692 syscalls, it's possible to isolate those applications in
1693 their own address space using seccomp. Once seccomp is
1694 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1695 and the task is only allowed to execute a few safe syscalls
1696 defined by each seccomp mode.
1698 config CC_STACKPROTECTOR
1699 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1700 depends on EXPERIMENTAL
1702 This option turns on the -fstack-protector GCC feature. This
1703 feature puts, at the beginning of functions, a canary value on
1704 the stack just before the return address, and validates
1705 the value just before actually returning. Stack based buffer
1706 overflows (that need to overwrite this return address) now also
1707 overwrite the canary, which gets detected and the attack is then
1708 neutralized via a kernel panic.
1709 This feature requires gcc version 4.2 or above.
1711 config DEPRECATED_PARAM_STRUCT
1712 bool "Provide old way to pass kernel parameters"
1714 This was deprecated in 2001 and announced to live on for 5 years.
1715 Some old boot loaders still use this way.
1722 bool "Flattened Device Tree support"
1724 select OF_EARLY_FLATTREE
1727 Include support for flattened device tree machine descriptions.
1729 # Compressed boot loader in ROM. Yes, we really want to ask about
1730 # TEXT and BSS so we preserve their values in the config files.
1731 config ZBOOT_ROM_TEXT
1732 hex "Compressed ROM boot loader base address"
1735 The physical address at which the ROM-able zImage is to be
1736 placed in the target. Platforms which normally make use of
1737 ROM-able zImage formats normally set this to a suitable
1738 value in their defconfig file.
1740 If ZBOOT_ROM is not enabled, this has no effect.
1742 config ZBOOT_ROM_BSS
1743 hex "Compressed ROM boot loader BSS address"
1746 The base address of an area of read/write memory in the target
1747 for the ROM-able zImage which must be available while the
1748 decompressor is running. It must be large enough to hold the
1749 entire decompressed kernel plus an additional 128 KiB.
1750 Platforms which normally make use of ROM-able zImage formats
1751 normally set this to a suitable value in their defconfig file.
1753 If ZBOOT_ROM is not enabled, this has no effect.
1756 bool "Compressed boot loader in ROM/flash"
1757 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1759 Say Y here if you intend to execute your compressed kernel image
1760 (zImage) directly from ROM or flash. If unsure, say N.
1763 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1764 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1765 default ZBOOT_ROM_NONE
1767 Include experimental SD/MMC loading code in the ROM-able zImage.
1768 With this enabled it is possible to write the the ROM-able zImage
1769 kernel image to an MMC or SD card and boot the kernel straight
1770 from the reset vector. At reset the processor Mask ROM will load
1771 the first part of the the ROM-able zImage which in turn loads the
1772 rest the kernel image to RAM.
1774 config ZBOOT_ROM_NONE
1775 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1777 Do not load image from SD or MMC
1779 config ZBOOT_ROM_MMCIF
1780 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1782 Load image from MMCIF hardware block.
1784 config ZBOOT_ROM_SH_MOBILE_SDHI
1785 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1787 Load image from SDHI hardware block
1792 string "Default kernel command string"
1795 On some architectures (EBSA110 and CATS), there is currently no way
1796 for the boot loader to pass arguments to the kernel. For these
1797 architectures, you should supply some command-line options at build
1798 time by entering them here. As a minimum, you should specify the
1799 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1802 prompt "Kernel command line type" if CMDLINE != ""
1803 default CMDLINE_FROM_BOOTLOADER
1805 config CMDLINE_FROM_BOOTLOADER
1806 bool "Use bootloader kernel arguments if available"
1808 Uses the command-line options passed by the boot loader. If
1809 the boot loader doesn't provide any, the default kernel command
1810 string provided in CMDLINE will be used.
1812 config CMDLINE_EXTEND
1813 bool "Extend bootloader kernel arguments"
1815 The command-line arguments provided by the boot loader will be
1816 appended to the default kernel command string.
1818 config CMDLINE_FORCE
1819 bool "Always use the default kernel command string"
1821 Always use the default kernel command string, even if the boot
1822 loader passes other arguments to the kernel.
1823 This is useful if you cannot or don't want to change the
1824 command-line options your boot loader passes to the kernel.
1828 bool "Kernel Execute-In-Place from ROM"
1829 depends on !ZBOOT_ROM
1831 Execute-In-Place allows the kernel to run from non-volatile storage
1832 directly addressable by the CPU, such as NOR flash. This saves RAM
1833 space since the text section of the kernel is not loaded from flash
1834 to RAM. Read-write sections, such as the data section and stack,
1835 are still copied to RAM. The XIP kernel is not compressed since
1836 it has to run directly from flash, so it will take more space to
1837 store it. The flash address used to link the kernel object files,
1838 and for storing it, is configuration dependent. Therefore, if you
1839 say Y here, you must know the proper physical address where to
1840 store the kernel image depending on your own flash memory usage.
1842 Also note that the make target becomes "make xipImage" rather than
1843 "make zImage" or "make Image". The final kernel binary to put in
1844 ROM memory will be arch/arm/boot/xipImage.
1848 config XIP_PHYS_ADDR
1849 hex "XIP Kernel Physical Location"
1850 depends on XIP_KERNEL
1851 default "0x00080000"
1853 This is the physical address in your flash memory the kernel will
1854 be linked for and stored to. This address is dependent on your
1858 bool "Kexec system call (EXPERIMENTAL)"
1859 depends on EXPERIMENTAL
1861 kexec is a system call that implements the ability to shutdown your
1862 current kernel, and to start another kernel. It is like a reboot
1863 but it is independent of the system firmware. And like a reboot
1864 you can start any kernel with it, not just Linux.
1866 It is an ongoing process to be certain the hardware in a machine
1867 is properly shutdown, so do not be surprised if this code does not
1868 initially work for you. It may help to enable device hotplugging
1872 bool "Export atags in procfs"
1876 Should the atags used to boot the kernel be exported in an "atags"
1877 file in procfs. Useful with kexec.
1880 bool "Build kdump crash kernel (EXPERIMENTAL)"
1881 depends on EXPERIMENTAL
1883 Generate crash dump after being started by kexec. This should
1884 be normally only set in special crash dump kernels which are
1885 loaded in the main kernel with kexec-tools into a specially
1886 reserved region and then later executed after a crash by
1887 kdump/kexec. The crash dump kernel must be compiled to a
1888 memory address not used by the main kernel
1890 For more details see Documentation/kdump/kdump.txt
1892 config AUTO_ZRELADDR
1893 bool "Auto calculation of the decompressed kernel image address"
1894 depends on !ZBOOT_ROM && !ARCH_U300
1896 ZRELADDR is the physical address where the decompressed kernel
1897 image will be placed. If AUTO_ZRELADDR is selected, the address
1898 will be determined at run-time by masking the current IP with
1899 0xf8000000. This assumes the zImage being placed in the first 128MB
1900 from start of memory.
1904 menu "CPU Power Management"
1908 source "drivers/cpufreq/Kconfig"
1911 tristate "CPUfreq driver for i.MX CPUs"
1912 depends on ARCH_MXC && CPU_FREQ
1914 This enables the CPUfreq driver for i.MX CPUs.
1916 config CPU_FREQ_SA1100
1919 config CPU_FREQ_SA1110
1922 config CPU_FREQ_INTEGRATOR
1923 tristate "CPUfreq driver for ARM Integrator CPUs"
1924 depends on ARCH_INTEGRATOR && CPU_FREQ
1927 This enables the CPUfreq driver for ARM Integrator CPUs.
1929 For details, take a look at <file:Documentation/cpu-freq>.
1935 depends on CPU_FREQ && ARCH_PXA && PXA25x
1937 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1942 Internal configuration node for common cpufreq on Samsung SoC
1944 config CPU_FREQ_S3C24XX
1945 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1946 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1949 This enables the CPUfreq driver for the Samsung S3C24XX family
1952 For details, take a look at <file:Documentation/cpu-freq>.
1956 config CPU_FREQ_S3C24XX_PLL
1957 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1958 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1960 Compile in support for changing the PLL frequency from the
1961 S3C24XX series CPUfreq driver. The PLL takes time to settle
1962 after a frequency change, so by default it is not enabled.
1964 This also means that the PLL tables for the selected CPU(s) will
1965 be built which may increase the size of the kernel image.
1967 config CPU_FREQ_S3C24XX_DEBUG
1968 bool "Debug CPUfreq Samsung driver core"
1969 depends on CPU_FREQ_S3C24XX
1971 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1973 config CPU_FREQ_S3C24XX_IODEBUG
1974 bool "Debug CPUfreq Samsung driver IO timing"
1975 depends on CPU_FREQ_S3C24XX
1977 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1979 config CPU_FREQ_S3C24XX_DEBUGFS
1980 bool "Export debugfs for CPUFreq"
1981 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1983 Export status information via debugfs.
1987 source "drivers/cpuidle/Kconfig"
1991 menu "Floating point emulation"
1993 comment "At least one emulation must be selected"
1996 bool "NWFPE math emulation"
1997 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1999 Say Y to include the NWFPE floating point emulator in the kernel.
2000 This is necessary to run most binaries. Linux does not currently
2001 support floating point hardware so you need to say Y here even if
2002 your machine has an FPA or floating point co-processor podule.
2004 You may say N here if you are going to load the Acorn FPEmulator
2005 early in the bootup.
2008 bool "Support extended precision"
2009 depends on FPE_NWFPE
2011 Say Y to include 80-bit support in the kernel floating-point
2012 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2013 Note that gcc does not generate 80-bit operations by default,
2014 so in most cases this option only enlarges the size of the
2015 floating point emulator without any good reason.
2017 You almost surely want to say N here.
2020 bool "FastFPE math emulation (EXPERIMENTAL)"
2021 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2023 Say Y here to include the FAST floating point emulator in the kernel.
2024 This is an experimental much faster emulator which now also has full
2025 precision for the mantissa. It does not support any exceptions.
2026 It is very simple, and approximately 3-6 times faster than NWFPE.
2028 It should be sufficient for most programs. It may be not suitable
2029 for scientific calculations, but you have to check this for yourself.
2030 If you do not feel you need a faster FP emulation you should better
2034 bool "VFP-format floating point maths"
2035 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2037 Say Y to include VFP support code in the kernel. This is needed
2038 if your hardware includes a VFP unit.
2040 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2041 release notes and additional status information.
2043 Say N if your target does not have VFP hardware.
2051 bool "Advanced SIMD (NEON) Extension support"
2052 depends on VFPv3 && CPU_V7
2054 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2059 menu "Userspace binary formats"
2061 source "fs/Kconfig.binfmt"
2064 tristate "RISC OS personality"
2067 Say Y here to include the kernel code necessary if you want to run
2068 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2069 experimental; if this sounds frightening, say N and sleep in peace.
2070 You can also say M here to compile this support as a module (which
2071 will be called arthur).
2075 menu "Power management options"
2077 source "kernel/power/Kconfig"
2079 config ARCH_SUSPEND_POSSIBLE
2080 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2081 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2082 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2085 config ARM_CPU_SUSPEND
2090 source "net/Kconfig"
2092 source "drivers/Kconfig"
2096 source "arch/arm/Kconfig.debug"
2098 source "security/Kconfig"
2100 source "crypto/Kconfig"
2102 source "lib/Kconfig"