5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
46 config SYS_SUPPORTS_APM_EMULATION
49 config HAVE_SCHED_CLOCK
55 config ARCH_USES_GETTIMEOFFSET
59 config GENERIC_CLOCKEVENTS
62 config GENERIC_CLOCKEVENTS_BROADCAST
64 depends on GENERIC_CLOCKEVENTS
73 select GENERIC_ALLOCATOR
84 The Extended Industry Standard Architecture (EISA) bus was
85 developed as an open alternative to the IBM MicroChannel bus.
87 The EISA bus provided some of the features of the IBM MicroChannel
88 bus while maintaining backward compatibility with cards made for
89 the older ISA bus. The EISA bus saw limited use between 1988 and
90 1995 when it was made obsolete by the PCI bus.
92 Say Y here if you are building a kernel for an EISA-based machine.
102 MicroChannel Architecture is found in some IBM PS/2 machines and
103 laptops. It is a bus system similar to PCI or ISA. See
104 <file:Documentation/mca.txt> (and especially the web page given
105 there) before attempting to build an MCA bus kernel.
107 config STACKTRACE_SUPPORT
111 config HAVE_LATENCYTOP_SUPPORT
116 config LOCKDEP_SUPPORT
120 config TRACE_IRQFLAGS_SUPPORT
124 config HARDIRQS_SW_RESEND
128 config GENERIC_IRQ_PROBE
132 config GENERIC_LOCKBREAK
135 depends on SMP && PREEMPT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config ARCH_HAS_CPU_IDLE_WAIT
160 config GENERIC_HWEIGHT
164 config GENERIC_CALIBRATE_DELAY
168 config ARCH_MAY_HAVE_PC_FDC
174 config NEED_DMA_MAP_STATE
177 config GENERIC_ISA_DMA
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
196 depends on EXPERIMENTAL
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt translation functions at runtime according to
201 the position of the kernel in system memory.
203 This can only be used with non-XIP with MMU kernels where
204 the base of physical memory is at a 16MB boundary.
206 config ARM_PATCH_PHYS_VIRT_16BIT
208 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
210 source "init/Kconfig"
212 source "kernel/Kconfig.freezer"
217 bool "MMU-based Paged Memory Management Support"
220 Select if you want MMU-based virtualised addressing space
221 support by paged memory management. If unsure, say 'Y'.
224 # The "ARM system type" choice list is ordered alphabetically by option
225 # text. Please add new entries in the option alphabetic order.
228 prompt "ARM system type"
229 default ARCH_VERSATILE
231 config ARCH_INTEGRATOR
232 bool "ARM Ltd. Integrator family"
234 select ARCH_HAS_CPUFREQ
237 select GENERIC_CLOCKEVENTS
238 select PLAT_VERSATILE
239 select PLAT_VERSATILE_FPGA_IRQ
241 Support for ARM's Integrator platform.
244 bool "ARM Ltd. RealView family"
248 select GENERIC_CLOCKEVENTS
249 select ARCH_WANT_OPTIONAL_GPIOLIB
250 select PLAT_VERSATILE
251 select PLAT_VERSATILE_CLCD
252 select ARM_TIMER_SP804
253 select GPIO_PL061 if GPIOLIB
255 This enables support for ARM Ltd RealView boards.
257 config ARCH_VERSATILE
258 bool "ARM Ltd. Versatile family"
263 select GENERIC_CLOCKEVENTS
264 select ARCH_WANT_OPTIONAL_GPIOLIB
265 select PLAT_VERSATILE
266 select PLAT_VERSATILE_CLCD
267 select PLAT_VERSATILE_FPGA_IRQ
268 select ARM_TIMER_SP804
270 This enables support for ARM Ltd Versatile board.
273 bool "ARM Ltd. Versatile Express family"
274 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select ARM_TIMER_SP804
278 select GENERIC_CLOCKEVENTS
280 select HAVE_PATA_PLATFORM
282 select PLAT_VERSATILE
283 select PLAT_VERSATILE_CLCD
285 This enables support for the ARM Ltd Versatile Express boards.
289 select ARCH_REQUIRE_GPIOLIB
292 This enables support for systems based on the Atmel AT91RM9200,
293 AT91SAM9 and AT91CAP9 processors.
296 bool "Broadcom BCMRING"
300 select ARM_TIMER_SP804
302 select GENERIC_CLOCKEVENTS
303 select ARCH_WANT_OPTIONAL_GPIOLIB
305 Support for Broadcom's BCMRing platform.
308 bool "Cirrus Logic CLPS711x/EP721x-based"
310 select ARCH_USES_GETTIMEOFFSET
312 Support for Cirrus Logic 711x/721x based boards.
315 bool "Cavium Networks CNS3XXX family"
317 select GENERIC_CLOCKEVENTS
319 select MIGHT_HAVE_PCI
320 select PCI_DOMAINS if PCI
322 Support for Cavium Networks CNS3XXX platform.
325 bool "Cortina Systems Gemini"
327 select ARCH_REQUIRE_GPIOLIB
328 select ARCH_USES_GETTIMEOFFSET
330 Support for the Cortina Systems Gemini family SoCs
337 select ARCH_USES_GETTIMEOFFSET
339 This is an evaluation board for the StrongARM processor available
340 from Digital. It has limited hardware on-board, including an
341 Ethernet interface, two PCMCIA sockets, two serial ports and a
350 select ARCH_REQUIRE_GPIOLIB
351 select ARCH_HAS_HOLES_MEMORYMODEL
352 select ARCH_USES_GETTIMEOFFSET
354 This enables support for the Cirrus EP93xx series of CPUs.
356 config ARCH_FOOTBRIDGE
360 select GENERIC_CLOCKEVENTS
362 Support for systems based on the DC21285 companion chip
363 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
366 bool "Freescale MXC/iMX-based"
367 select GENERIC_CLOCKEVENTS
368 select ARCH_REQUIRE_GPIOLIB
371 select HAVE_SCHED_CLOCK
373 Support for Freescale MXC/iMX-based family of processors
376 bool "Freescale MXS-based"
377 select GENERIC_CLOCKEVENTS
378 select ARCH_REQUIRE_GPIOLIB
382 Support for Freescale MXS-based family of processors
385 bool "Hilscher NetX based"
389 select GENERIC_CLOCKEVENTS
391 This enables support for systems based on the Hilscher NetX Soc
394 bool "Hynix HMS720x-based"
397 select ARCH_USES_GETTIMEOFFSET
399 This enables support for systems based on the Hynix HMS720x
407 select ARCH_SUPPORTS_MSI
410 Support for Intel's IOP13XX (XScale) family of processors.
418 select ARCH_REQUIRE_GPIOLIB
420 Support for Intel's 80219 and IOP32X (XScale) family of
429 select ARCH_REQUIRE_GPIOLIB
431 Support for Intel's IOP33X (XScale) family of processors.
438 select ARCH_USES_GETTIMEOFFSET
440 Support for Intel's IXP23xx (XScale) family of processors.
443 bool "IXP2400/2800-based"
447 select ARCH_USES_GETTIMEOFFSET
449 Support for Intel's IXP2400/2800 (XScale) family of processors.
457 select GENERIC_CLOCKEVENTS
458 select HAVE_SCHED_CLOCK
459 select MIGHT_HAVE_PCI
460 select DMABOUNCE if PCI
462 Support for Intel's IXP4XX (XScale) family of processors.
468 select ARCH_REQUIRE_GPIOLIB
469 select GENERIC_CLOCKEVENTS
472 Support for the Marvell Dove SoC 88AP510
475 bool "Marvell Kirkwood"
478 select ARCH_REQUIRE_GPIOLIB
479 select GENERIC_CLOCKEVENTS
482 Support for the following Marvell Kirkwood series SoCs:
483 88F6180, 88F6192 and 88F6281.
486 bool "Marvell Loki (88RC8480)"
488 select GENERIC_CLOCKEVENTS
491 Support for the Marvell Loki (88RC8480) SoC.
497 select ARCH_REQUIRE_GPIOLIB
500 select USB_ARCH_HAS_OHCI
503 select GENERIC_CLOCKEVENTS
505 Support for the NXP LPC32XX family of processors
508 bool "Marvell MV78xx0"
511 select ARCH_REQUIRE_GPIOLIB
512 select GENERIC_CLOCKEVENTS
515 Support for the following Marvell MV78xx0 series SoCs:
523 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
527 Support for the following Marvell Orion 5x series SoCs:
528 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
529 Orion-2 (5281), Orion-1-90 (6183).
532 bool "Marvell PXA168/910/MMP2"
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
537 select HAVE_SCHED_CLOCK
542 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
545 bool "Micrel/Kendin KS8695"
547 select ARCH_REQUIRE_GPIOLIB
548 select ARCH_USES_GETTIMEOFFSET
550 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
551 System-on-Chip devices.
554 bool "NetSilicon NS9xxx"
557 select GENERIC_CLOCKEVENTS
560 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
563 <http://www.digi.com/products/microprocessors/index.jsp>
566 bool "Nuvoton W90X900 CPU"
568 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
573 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
574 At present, the w90x900 has been renamed nuc900, regarding
575 the ARM series product line, you can login the following
576 link address to know more.
578 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
579 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
582 bool "Nuvoton NUC93X CPU"
586 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
587 low-power and high performance MPEG-4/JPEG multimedia controller chip.
594 select GENERIC_CLOCKEVENTS
597 select HAVE_SCHED_CLOCK
598 select ARCH_HAS_BARRIERS if CACHE_L2X0
599 select ARCH_HAS_CPUFREQ
601 This enables support for NVIDIA Tegra based systems (Tegra APX,
602 Tegra 6xx and Tegra 2 series).
605 bool "Philips Nexperia PNX4008 Mobile"
608 select ARCH_USES_GETTIMEOFFSET
610 This enables support for Philips PNX4008 mobile platform.
613 bool "PXA2xx/PXA3xx-based"
616 select ARCH_HAS_CPUFREQ
619 select ARCH_REQUIRE_GPIOLIB
620 select GENERIC_CLOCKEVENTS
621 select HAVE_SCHED_CLOCK
626 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
631 select GENERIC_CLOCKEVENTS
632 select ARCH_REQUIRE_GPIOLIB
635 Support for Qualcomm MSM/QSD based systems. This runs on the
636 apps processor of the MSM/QSD and depends on a shared memory
637 interface to the modem processor which runs the baseband
638 stack and controls some vital subsystems
639 (clock and power control, etc).
642 bool "Renesas SH-Mobile / R-Mobile"
645 select GENERIC_CLOCKEVENTS
648 select MULTI_IRQ_HANDLER
650 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
657 select ARCH_MAY_HAVE_PC_FDC
658 select HAVE_PATA_PLATFORM
661 select ARCH_SPARSEMEM_ENABLE
662 select ARCH_USES_GETTIMEOFFSET
664 On the Acorn Risc-PC, Linux can support the internal IDE disk and
665 CD-ROM interface, serial and parallel port, and the floppy drive.
672 select ARCH_SPARSEMEM_ENABLE
674 select ARCH_HAS_CPUFREQ
676 select GENERIC_CLOCKEVENTS
678 select HAVE_SCHED_CLOCK
680 select ARCH_REQUIRE_GPIOLIB
682 Support for StrongARM 11x0 based boards.
685 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
687 select ARCH_HAS_CPUFREQ
689 select ARCH_USES_GETTIMEOFFSET
690 select HAVE_S3C2410_I2C if I2C
692 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
693 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
694 the Samsung SMDK2410 development board (and derivatives).
696 Note, the S3C2416 and the S3C2450 are so close that they even share
697 the same SoC ID code. This means that there is no separate machine
698 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
701 bool "Samsung S3C64XX"
707 select ARCH_USES_GETTIMEOFFSET
708 select ARCH_HAS_CPUFREQ
709 select ARCH_REQUIRE_GPIOLIB
710 select SAMSUNG_CLKSRC
711 select SAMSUNG_IRQ_VIC_TIMER
712 select SAMSUNG_IRQ_UART
713 select S3C_GPIO_TRACK
714 select S3C_GPIO_PULL_UPDOWN
715 select S3C_GPIO_CFG_S3C24XX
716 select S3C_GPIO_CFG_S3C64XX
718 select USB_ARCH_HAS_OHCI
719 select SAMSUNG_GPIOLIB_4BIT
720 select HAVE_S3C2410_I2C if I2C
721 select HAVE_S3C2410_WATCHDOG if WATCHDOG
723 Samsung S3C64XX series based systems
726 bool "Samsung S5P6440 S5P6450"
730 select HAVE_S3C2410_WATCHDOG if WATCHDOG
731 select GENERIC_CLOCKEVENTS
732 select HAVE_SCHED_CLOCK
733 select HAVE_S3C2410_I2C if I2C
734 select HAVE_S3C_RTC if RTC_CLASS
736 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
740 bool "Samsung S5P6442"
744 select ARCH_USES_GETTIMEOFFSET
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 Samsung S5P6442 CPU based systems
750 bool "Samsung S5PC100"
754 select ARM_L1_CACHE_SHIFT_6
755 select ARCH_USES_GETTIMEOFFSET
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C_RTC if RTC_CLASS
758 select HAVE_S3C2410_WATCHDOG if WATCHDOG
760 Samsung S5PC100 series based systems
763 bool "Samsung S5PV210/S5PC110"
765 select ARCH_SPARSEMEM_ENABLE
768 select ARM_L1_CACHE_SHIFT_6
769 select ARCH_HAS_CPUFREQ
770 select GENERIC_CLOCKEVENTS
771 select HAVE_SCHED_CLOCK
772 select HAVE_S3C2410_I2C if I2C
773 select HAVE_S3C_RTC if RTC_CLASS
774 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 Samsung S5PV210/S5PC110 series based systems
779 bool "Samsung EXYNOS4"
781 select ARCH_SPARSEMEM_ENABLE
784 select ARCH_HAS_CPUFREQ
785 select GENERIC_CLOCKEVENTS
786 select HAVE_S3C_RTC if RTC_CLASS
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 Samsung EXYNOS4 series based systems
799 select ARCH_USES_GETTIMEOFFSET
801 Support for the StrongARM based Digital DNARD machine, also known
802 as "Shark" (<http://www.shark-linux.de/shark.html>).
805 bool "Telechips TCC ARM926-based systems"
810 select GENERIC_CLOCKEVENTS
812 Support for Telechips TCC ARM926-based systems.
815 bool "ST-Ericsson U300 Series"
819 select HAVE_SCHED_CLOCK
823 select GENERIC_CLOCKEVENTS
827 Support for ST-Ericsson U300 series mobile platforms.
830 bool "ST-Ericsson U8500 Series"
833 select GENERIC_CLOCKEVENTS
835 select ARCH_REQUIRE_GPIOLIB
836 select ARCH_HAS_CPUFREQ
838 Support for ST-Ericsson's Ux500 architecture
841 bool "STMicroelectronics Nomadik"
846 select GENERIC_CLOCKEVENTS
847 select ARCH_REQUIRE_GPIOLIB
849 Support for the Nomadik platform by ST-Ericsson
853 select GENERIC_CLOCKEVENTS
854 select ARCH_REQUIRE_GPIOLIB
858 select GENERIC_ALLOCATOR
859 select ARCH_HAS_HOLES_MEMORYMODEL
861 Support for TI's DaVinci platform.
866 select ARCH_REQUIRE_GPIOLIB
867 select ARCH_HAS_CPUFREQ
868 select GENERIC_CLOCKEVENTS
869 select HAVE_SCHED_CLOCK
870 select ARCH_HAS_HOLES_MEMORYMODEL
872 Support for TI's OMAP platform (OMAP1/2/3/4).
877 select ARCH_REQUIRE_GPIOLIB
880 select GENERIC_CLOCKEVENTS
883 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
886 bool "VIA/WonderMedia 85xx"
889 select ARCH_HAS_CPUFREQ
890 select GENERIC_CLOCKEVENTS
891 select ARCH_REQUIRE_GPIOLIB
894 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
898 # This is sorted alphabetically by mach-* pathname. However, plat-*
899 # Kconfigs may be included either alphabetically (according to the
900 # plat- suffix) or along side the corresponding mach-* source.
902 source "arch/arm/mach-at91/Kconfig"
904 source "arch/arm/mach-bcmring/Kconfig"
906 source "arch/arm/mach-clps711x/Kconfig"
908 source "arch/arm/mach-cns3xxx/Kconfig"
910 source "arch/arm/mach-davinci/Kconfig"
912 source "arch/arm/mach-dove/Kconfig"
914 source "arch/arm/mach-ep93xx/Kconfig"
916 source "arch/arm/mach-footbridge/Kconfig"
918 source "arch/arm/mach-gemini/Kconfig"
920 source "arch/arm/mach-h720x/Kconfig"
922 source "arch/arm/mach-integrator/Kconfig"
924 source "arch/arm/mach-iop32x/Kconfig"
926 source "arch/arm/mach-iop33x/Kconfig"
928 source "arch/arm/mach-iop13xx/Kconfig"
930 source "arch/arm/mach-ixp4xx/Kconfig"
932 source "arch/arm/mach-ixp2000/Kconfig"
934 source "arch/arm/mach-ixp23xx/Kconfig"
936 source "arch/arm/mach-kirkwood/Kconfig"
938 source "arch/arm/mach-ks8695/Kconfig"
940 source "arch/arm/mach-loki/Kconfig"
942 source "arch/arm/mach-lpc32xx/Kconfig"
944 source "arch/arm/mach-msm/Kconfig"
946 source "arch/arm/mach-mv78xx0/Kconfig"
948 source "arch/arm/plat-mxc/Kconfig"
950 source "arch/arm/mach-mxs/Kconfig"
952 source "arch/arm/mach-netx/Kconfig"
954 source "arch/arm/mach-nomadik/Kconfig"
955 source "arch/arm/plat-nomadik/Kconfig"
957 source "arch/arm/mach-ns9xxx/Kconfig"
959 source "arch/arm/mach-nuc93x/Kconfig"
961 source "arch/arm/plat-omap/Kconfig"
963 source "arch/arm/mach-omap1/Kconfig"
965 source "arch/arm/mach-omap2/Kconfig"
967 source "arch/arm/mach-orion5x/Kconfig"
969 source "arch/arm/mach-pxa/Kconfig"
970 source "arch/arm/plat-pxa/Kconfig"
972 source "arch/arm/mach-mmp/Kconfig"
974 source "arch/arm/mach-realview/Kconfig"
976 source "arch/arm/mach-sa1100/Kconfig"
978 source "arch/arm/plat-samsung/Kconfig"
979 source "arch/arm/plat-s3c24xx/Kconfig"
980 source "arch/arm/plat-s5p/Kconfig"
982 source "arch/arm/plat-spear/Kconfig"
984 source "arch/arm/plat-tcc/Kconfig"
987 source "arch/arm/mach-s3c2400/Kconfig"
988 source "arch/arm/mach-s3c2410/Kconfig"
989 source "arch/arm/mach-s3c2412/Kconfig"
990 source "arch/arm/mach-s3c2416/Kconfig"
991 source "arch/arm/mach-s3c2440/Kconfig"
992 source "arch/arm/mach-s3c2443/Kconfig"
996 source "arch/arm/mach-s3c64xx/Kconfig"
999 source "arch/arm/mach-s5p64x0/Kconfig"
1001 source "arch/arm/mach-s5p6442/Kconfig"
1003 source "arch/arm/mach-s5pc100/Kconfig"
1005 source "arch/arm/mach-s5pv210/Kconfig"
1007 source "arch/arm/mach-exynos4/Kconfig"
1009 source "arch/arm/mach-shmobile/Kconfig"
1011 source "arch/arm/mach-tegra/Kconfig"
1013 source "arch/arm/mach-u300/Kconfig"
1015 source "arch/arm/mach-ux500/Kconfig"
1017 source "arch/arm/mach-versatile/Kconfig"
1019 source "arch/arm/mach-vexpress/Kconfig"
1020 source "arch/arm/plat-versatile/Kconfig"
1022 source "arch/arm/mach-vt8500/Kconfig"
1024 source "arch/arm/mach-w90x900/Kconfig"
1026 # Definitions to make life easier
1032 select GENERIC_CLOCKEVENTS
1033 select HAVE_SCHED_CLOCK
1038 select HAVE_SCHED_CLOCK
1043 config PLAT_VERSATILE
1046 config ARM_TIMER_SP804
1050 source arch/arm/mm/Kconfig
1053 bool "Enable iWMMXt support"
1054 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1055 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1057 Enable support for iWMMXt context switching at run time if
1058 running on a CPU that supports it.
1060 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1063 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1067 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1068 (!ARCH_OMAP3 || OMAP3_EMU)
1072 config MULTI_IRQ_HANDLER
1075 Allow each machine to specify it's own IRQ handler at run time.
1078 source "arch/arm/Kconfig-nommu"
1081 config ARM_ERRATA_411920
1082 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1083 depends on CPU_V6 || CPU_V6K
1085 Invalidation of the Instruction Cache operation can
1086 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1087 It does not affect the MPCore. This option enables the ARM Ltd.
1088 recommended workaround.
1090 config ARM_ERRATA_430973
1091 bool "ARM errata: Stale prediction on replaced interworking branch"
1094 This option enables the workaround for the 430973 Cortex-A8
1095 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1096 interworking branch is replaced with another code sequence at the
1097 same virtual address, whether due to self-modifying code or virtual
1098 to physical address re-mapping, Cortex-A8 does not recover from the
1099 stale interworking branch prediction. This results in Cortex-A8
1100 executing the new code sequence in the incorrect ARM or Thumb state.
1101 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1102 and also flushes the branch target cache at every context switch.
1103 Note that setting specific bits in the ACTLR register may not be
1104 available in non-secure mode.
1106 config ARM_ERRATA_458693
1107 bool "ARM errata: Processor deadlock when a false hazard is created"
1110 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1111 erratum. For very specific sequences of memory operations, it is
1112 possible for a hazard condition intended for a cache line to instead
1113 be incorrectly associated with a different cache line. This false
1114 hazard might then cause a processor deadlock. The workaround enables
1115 the L1 caching of the NEON accesses and disables the PLD instruction
1116 in the ACTLR register. Note that setting specific bits in the ACTLR
1117 register may not be available in non-secure mode.
1119 config ARM_ERRATA_460075
1120 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1123 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1124 erratum. Any asynchronous access to the L2 cache may encounter a
1125 situation in which recent store transactions to the L2 cache are lost
1126 and overwritten with stale memory contents from external memory. The
1127 workaround disables the write-allocate mode for the L2 cache via the
1128 ACTLR register. Note that setting specific bits in the ACTLR register
1129 may not be available in non-secure mode.
1131 config ARM_ERRATA_742230
1132 bool "ARM errata: DMB operation may be faulty"
1133 depends on CPU_V7 && SMP
1135 This option enables the workaround for the 742230 Cortex-A9
1136 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1137 between two write operations may not ensure the correct visibility
1138 ordering of the two writes. This workaround sets a specific bit in
1139 the diagnostic register of the Cortex-A9 which causes the DMB
1140 instruction to behave as a DSB, ensuring the correct behaviour of
1143 config ARM_ERRATA_742231
1144 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1145 depends on CPU_V7 && SMP
1147 This option enables the workaround for the 742231 Cortex-A9
1148 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1149 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1150 accessing some data located in the same cache line, may get corrupted
1151 data due to bad handling of the address hazard when the line gets
1152 replaced from one of the CPUs at the same time as another CPU is
1153 accessing it. This workaround sets specific bits in the diagnostic
1154 register of the Cortex-A9 which reduces the linefill issuing
1155 capabilities of the processor.
1157 config PL310_ERRATA_588369
1158 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1159 depends on CACHE_L2X0
1161 The PL310 L2 cache controller implements three types of Clean &
1162 Invalidate maintenance operations: by Physical Address
1163 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1164 They are architecturally defined to behave as the execution of a
1165 clean operation followed immediately by an invalidate operation,
1166 both performing to the same memory location. This functionality
1167 is not correctly implemented in PL310 as clean lines are not
1168 invalidated as a result of these operations.
1170 config ARM_ERRATA_720789
1171 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1172 depends on CPU_V7 && SMP
1174 This option enables the workaround for the 720789 Cortex-A9 (prior to
1175 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1176 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1177 As a consequence of this erratum, some TLB entries which should be
1178 invalidated are not, resulting in an incoherency in the system page
1179 tables. The workaround changes the TLB flushing routines to invalidate
1180 entries regardless of the ASID.
1182 config PL310_ERRATA_727915
1183 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1184 depends on CACHE_L2X0
1186 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1187 operation (offset 0x7FC). This operation runs in background so that
1188 PL310 can handle normal accesses while it is in progress. Under very
1189 rare circumstances, due to this erratum, write data can be lost when
1190 PL310 treats a cacheable write transaction during a Clean &
1191 Invalidate by Way operation.
1193 config ARM_ERRATA_743622
1194 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1197 This option enables the workaround for the 743622 Cortex-A9
1198 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1199 optimisation in the Cortex-A9 Store Buffer may lead to data
1200 corruption. This workaround sets a specific bit in the diagnostic
1201 register of the Cortex-A9 which disables the Store Buffer
1202 optimisation, preventing the defect from occurring. This has no
1203 visible impact on the overall performance or power consumption of the
1206 config ARM_ERRATA_751472
1207 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1208 depends on CPU_V7 && SMP
1210 This option enables the workaround for the 751472 Cortex-A9 (prior
1211 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1212 completion of a following broadcasted operation if the second
1213 operation is received by a CPU before the ICIALLUIS has completed,
1214 potentially leading to corrupted entries in the cache or TLB.
1216 config ARM_ERRATA_753970
1217 bool "ARM errata: cache sync operation may be faulty"
1218 depends on CACHE_PL310
1220 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1222 Under some condition the effect of cache sync operation on
1223 the store buffer still remains when the operation completes.
1224 This means that the store buffer is always asked to drain and
1225 this prevents it from merging any further writes. The workaround
1226 is to replace the normal offset of cache sync operation (0x730)
1227 by another offset targeting an unmapped PL310 register 0x740.
1228 This has the same effect as the cache sync operation: store buffer
1229 drain and waiting for all buffers empty.
1231 config ARM_ERRATA_754322
1232 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1235 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1236 r3p*) erratum. A speculative memory access may cause a page table walk
1237 which starts prior to an ASID switch but completes afterwards. This
1238 can populate the micro-TLB with a stale entry which may be hit with
1239 the new ASID. This workaround places two dsb instructions in the mm
1240 switching code so that no page table walks can cross the ASID switch.
1242 config ARM_ERRATA_754327
1243 bool "ARM errata: no automatic Store Buffer drain"
1244 depends on CPU_V7 && SMP
1246 This option enables the workaround for the 754327 Cortex-A9 (prior to
1247 r2p0) erratum. The Store Buffer does not have any automatic draining
1248 mechanism and therefore a livelock may occur if an external agent
1249 continuously polls a memory location waiting to observe an update.
1250 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1251 written polling loops from denying visibility of updates to memory.
1255 source "arch/arm/common/Kconfig"
1265 Find out whether you have ISA slots on your motherboard. ISA is the
1266 name of a bus system, i.e. the way the CPU talks to the other stuff
1267 inside your box. Other bus systems are PCI, EISA, MicroChannel
1268 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1269 newer boards don't support it. If you have ISA, say Y, otherwise N.
1271 # Select ISA DMA controller support
1276 # Select ISA DMA interface
1281 bool "PCI support" if MIGHT_HAVE_PCI
1283 Find out whether you have a PCI motherboard. PCI is the name of a
1284 bus system, i.e. the way the CPU talks to the other stuff inside
1285 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1286 VESA. If you have PCI, say Y, otherwise N.
1292 config PCI_NANOENGINE
1293 bool "BSE nanoEngine PCI support"
1294 depends on SA1100_NANOENGINE
1296 Enable PCI on the BSE nanoEngine board.
1301 # Select the host bridge type
1302 config PCI_HOST_VIA82C505
1304 depends on PCI && ARCH_SHARK
1307 config PCI_HOST_ITE8152
1309 depends on PCI && MACH_ARMCORE
1313 source "drivers/pci/Kconfig"
1315 source "drivers/pcmcia/Kconfig"
1319 menu "Kernel Features"
1321 source "kernel/time/Kconfig"
1324 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1325 depends on EXPERIMENTAL
1326 depends on CPU_V6K || CPU_V7
1327 depends on GENERIC_CLOCKEVENTS
1328 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1329 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1330 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1331 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1332 select USE_GENERIC_SMP_HELPERS
1333 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1335 This enables support for systems with more than one CPU. If you have
1336 a system with only one CPU, like most personal computers, say N. If
1337 you have a system with more than one CPU, say Y.
1339 If you say N here, the kernel will run on single and multiprocessor
1340 machines, but will use only one CPU of a multiprocessor machine. If
1341 you say Y here, the kernel will run on many, but not all, single
1342 processor machines. On a single processor machine, the kernel will
1343 run faster if you say N here.
1345 See also <file:Documentation/i386/IO-APIC.txt>,
1346 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1347 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1349 If you don't know what to do here, say N.
1352 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1353 depends on EXPERIMENTAL
1354 depends on SMP && !XIP_KERNEL
1357 SMP kernels contain instructions which fail on non-SMP processors.
1358 Enabling this option allows the kernel to modify itself to make
1359 these instructions safe. Disabling it allows about 1K of space
1362 If you don't know what to do here, say Y.
1368 This option enables support for the ARM system coherency unit
1375 This options enables support for the ARM timer and watchdog unit
1378 prompt "Memory split"
1381 Select the desired split between kernel and user memory.
1383 If you are not absolutely sure what you are doing, leave this
1387 bool "3G/1G user/kernel split"
1389 bool "2G/2G user/kernel split"
1391 bool "1G/3G user/kernel split"
1396 default 0x40000000 if VMSPLIT_1G
1397 default 0x80000000 if VMSPLIT_2G
1401 int "Maximum number of CPUs (2-32)"
1407 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1408 depends on SMP && HOTPLUG && EXPERIMENTAL
1409 depends on !ARCH_MSM
1411 Say Y here to experiment with turning CPUs off and on. CPUs
1412 can be controlled through /sys/devices/system/cpu.
1415 bool "Use local timer interrupts"
1418 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1420 Enable support for local timers on SMP platforms, rather then the
1421 legacy IPI broadcast method. Local timers allows the system
1422 accounting to be spread across the timer interval, preventing a
1423 "thundering herd" at every timer tick.
1425 source kernel/Kconfig.preempt
1429 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1430 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1431 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1432 default AT91_TIMER_HZ if ARCH_AT91
1433 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1436 config THUMB2_KERNEL
1437 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1438 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1440 select ARM_ASM_UNIFIED
1442 By enabling this option, the kernel will be compiled in
1443 Thumb-2 mode. A compiler/assembler that understand the unified
1444 ARM-Thumb syntax is needed.
1448 config THUMB2_AVOID_R_ARM_THM_JUMP11
1449 bool "Work around buggy Thumb-2 short branch relocations in gas"
1450 depends on THUMB2_KERNEL && MODULES
1453 Various binutils versions can resolve Thumb-2 branches to
1454 locally-defined, preemptible global symbols as short-range "b.n"
1455 branch instructions.
1457 This is a problem, because there's no guarantee the final
1458 destination of the symbol, or any candidate locations for a
1459 trampoline, are within range of the branch. For this reason, the
1460 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1461 relocation in modules at all, and it makes little sense to add
1464 The symptom is that the kernel fails with an "unsupported
1465 relocation" error when loading some modules.
1467 Until fixed tools are available, passing
1468 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1469 code which hits this problem, at the cost of a bit of extra runtime
1470 stack usage in some cases.
1472 The problem is described in more detail at:
1473 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1475 Only Thumb-2 kernels are affected.
1477 Unless you are sure your tools don't have this problem, say Y.
1479 config ARM_ASM_UNIFIED
1483 bool "Use the ARM EABI to compile the kernel"
1485 This option allows for the kernel to be compiled using the latest
1486 ARM ABI (aka EABI). This is only useful if you are using a user
1487 space environment that is also compiled with EABI.
1489 Since there are major incompatibilities between the legacy ABI and
1490 EABI, especially with regard to structure member alignment, this
1491 option also changes the kernel syscall calling convention to
1492 disambiguate both ABIs and allow for backward compatibility support
1493 (selected with CONFIG_OABI_COMPAT).
1495 To use this you need GCC version 4.0.0 or later.
1498 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1499 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1502 This option preserves the old syscall interface along with the
1503 new (ARM EABI) one. It also provides a compatibility layer to
1504 intercept syscalls that have structure arguments which layout
1505 in memory differs between the legacy ABI and the new ARM EABI
1506 (only for non "thumb" binaries). This option adds a tiny
1507 overhead to all syscalls and produces a slightly larger kernel.
1508 If you know you'll be using only pure EABI user space then you
1509 can say N here. If this option is not selected and you attempt
1510 to execute a legacy ABI binary then the result will be
1511 UNPREDICTABLE (in fact it can be predicted that it won't work
1512 at all). If in doubt say Y.
1514 config ARCH_HAS_HOLES_MEMORYMODEL
1517 config ARCH_SPARSEMEM_ENABLE
1520 config ARCH_SPARSEMEM_DEFAULT
1521 def_bool ARCH_SPARSEMEM_ENABLE
1523 config ARCH_SELECT_MEMORY_MODEL
1524 def_bool ARCH_SPARSEMEM_ENABLE
1527 bool "High Memory Support (EXPERIMENTAL)"
1528 depends on MMU && EXPERIMENTAL
1530 The address space of ARM processors is only 4 Gigabytes large
1531 and it has to accommodate user address space, kernel address
1532 space as well as some memory mapped IO. That means that, if you
1533 have a large amount of physical memory and/or IO, not all of the
1534 memory can be "permanently mapped" by the kernel. The physical
1535 memory that is not permanently mapped is called "high memory".
1537 Depending on the selected kernel/user memory split, minimum
1538 vmalloc space and actual amount of RAM, you may not need this
1539 option which should result in a slightly faster kernel.
1544 bool "Allocate 2nd-level pagetables from highmem"
1547 config HW_PERF_EVENTS
1548 bool "Enable hardware performance counter support for perf events"
1549 depends on PERF_EVENTS && CPU_HAS_PMU
1552 Enable hardware performance counter support for perf events. If
1553 disabled, perf events will use software events only.
1557 config FORCE_MAX_ZONEORDER
1558 int "Maximum zone order" if ARCH_SHMOBILE
1559 range 11 64 if ARCH_SHMOBILE
1560 default "9" if SA1111
1563 The kernel memory allocator divides physically contiguous memory
1564 blocks into "zones", where each zone is a power of two number of
1565 pages. This option selects the largest power of two that the kernel
1566 keeps in the memory allocator. If you need to allocate very large
1567 blocks of physically contiguous memory, then you may need to
1568 increase this value.
1570 This config option is actually maximum order plus one. For example,
1571 a value of 11 means that the largest free memory block is 2^10 pages.
1574 bool "Timer and CPU usage LEDs"
1575 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1576 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1577 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1578 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1579 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1580 ARCH_AT91 || ARCH_DAVINCI || \
1581 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1583 If you say Y here, the LEDs on your machine will be used
1584 to provide useful information about your current system status.
1586 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1587 be able to select which LEDs are active using the options below. If
1588 you are compiling a kernel for the EBSA-110 or the LART however, the
1589 red LED will simply flash regularly to indicate that the system is
1590 still functional. It is safe to say Y here if you have a CATS
1591 system, but the driver will do nothing.
1594 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1595 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1596 || MACH_OMAP_PERSEUS2
1598 depends on !GENERIC_CLOCKEVENTS
1599 default y if ARCH_EBSA110
1601 If you say Y here, one of the system LEDs (the green one on the
1602 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1603 will flash regularly to indicate that the system is still
1604 operational. This is mainly useful to kernel hackers who are
1605 debugging unstable kernels.
1607 The LART uses the same LED for both Timer LED and CPU usage LED
1608 functions. You may choose to use both, but the Timer LED function
1609 will overrule the CPU usage LED.
1612 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1614 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1615 || MACH_OMAP_PERSEUS2
1618 If you say Y here, the red LED will be used to give a good real
1619 time indication of CPU usage, by lighting whenever the idle task
1620 is not currently executing.
1622 The LART uses the same LED for both Timer LED and CPU usage LED
1623 functions. You may choose to use both, but the Timer LED function
1624 will overrule the CPU usage LED.
1626 config ALIGNMENT_TRAP
1628 depends on CPU_CP15_MMU
1629 default y if !ARCH_EBSA110
1630 select HAVE_PROC_CPU if PROC_FS
1632 ARM processors cannot fetch/store information which is not
1633 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1634 address divisible by 4. On 32-bit ARM processors, these non-aligned
1635 fetch/store instructions will be emulated in software if you say
1636 here, which has a severe performance impact. This is necessary for
1637 correct operation of some network protocols. With an IP-only
1638 configuration it is safe to say N, otherwise say Y.
1640 config UACCESS_WITH_MEMCPY
1641 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1642 depends on MMU && EXPERIMENTAL
1643 default y if CPU_FEROCEON
1645 Implement faster copy_to_user and clear_user methods for CPU
1646 cores where a 8-word STM instruction give significantly higher
1647 memory write throughput than a sequence of individual 32bit stores.
1649 A possible side effect is a slight increase in scheduling latency
1650 between threads sharing the same address space if they invoke
1651 such copy operations with large buffers.
1653 However, if the CPU data cache is using a write-allocate mode,
1654 this option is unlikely to provide any performance gain.
1658 prompt "Enable seccomp to safely compute untrusted bytecode"
1660 This kernel feature is useful for number crunching applications
1661 that may need to compute untrusted bytecode during their
1662 execution. By using pipes or other transports made available to
1663 the process as file descriptors supporting the read/write
1664 syscalls, it's possible to isolate those applications in
1665 their own address space using seccomp. Once seccomp is
1666 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1667 and the task is only allowed to execute a few safe syscalls
1668 defined by each seccomp mode.
1670 config CC_STACKPROTECTOR
1671 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1672 depends on EXPERIMENTAL
1674 This option turns on the -fstack-protector GCC feature. This
1675 feature puts, at the beginning of functions, a canary value on
1676 the stack just before the return address, and validates
1677 the value just before actually returning. Stack based buffer
1678 overflows (that need to overwrite this return address) now also
1679 overwrite the canary, which gets detected and the attack is then
1680 neutralized via a kernel panic.
1681 This feature requires gcc version 4.2 or above.
1683 config DEPRECATED_PARAM_STRUCT
1684 bool "Provide old way to pass kernel parameters"
1686 This was deprecated in 2001 and announced to live on for 5 years.
1687 Some old boot loaders still use this way.
1693 # Compressed boot loader in ROM. Yes, we really want to ask about
1694 # TEXT and BSS so we preserve their values in the config files.
1695 config ZBOOT_ROM_TEXT
1696 hex "Compressed ROM boot loader base address"
1699 The physical address at which the ROM-able zImage is to be
1700 placed in the target. Platforms which normally make use of
1701 ROM-able zImage formats normally set this to a suitable
1702 value in their defconfig file.
1704 If ZBOOT_ROM is not enabled, this has no effect.
1706 config ZBOOT_ROM_BSS
1707 hex "Compressed ROM boot loader BSS address"
1710 The base address of an area of read/write memory in the target
1711 for the ROM-able zImage which must be available while the
1712 decompressor is running. It must be large enough to hold the
1713 entire decompressed kernel plus an additional 128 KiB.
1714 Platforms which normally make use of ROM-able zImage formats
1715 normally set this to a suitable value in their defconfig file.
1717 If ZBOOT_ROM is not enabled, this has no effect.
1720 bool "Compressed boot loader in ROM/flash"
1721 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1723 Say Y here if you intend to execute your compressed kernel image
1724 (zImage) directly from ROM or flash. If unsure, say N.
1726 config ZBOOT_ROM_MMCIF
1727 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1728 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1730 Say Y here to include experimental MMCIF loading code in the
1731 ROM-able zImage. With this enabled it is possible to write the
1732 the ROM-able zImage kernel image to an MMC card and boot the
1733 kernel straight from the reset vector. At reset the processor
1734 Mask ROM will load the first part of the the ROM-able zImage
1735 which in turn loads the rest the kernel image to RAM using the
1736 MMCIF hardware block.
1739 string "Default kernel command string"
1742 On some architectures (EBSA110 and CATS), there is currently no way
1743 for the boot loader to pass arguments to the kernel. For these
1744 architectures, you should supply some command-line options at build
1745 time by entering them here. As a minimum, you should specify the
1746 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1748 config CMDLINE_FORCE
1749 bool "Always use the default kernel command string"
1750 depends on CMDLINE != ""
1752 Always use the default kernel command string, even if the boot
1753 loader passes other arguments to the kernel.
1754 This is useful if you cannot or don't want to change the
1755 command-line options your boot loader passes to the kernel.
1760 bool "Kernel Execute-In-Place from ROM"
1761 depends on !ZBOOT_ROM
1763 Execute-In-Place allows the kernel to run from non-volatile storage
1764 directly addressable by the CPU, such as NOR flash. This saves RAM
1765 space since the text section of the kernel is not loaded from flash
1766 to RAM. Read-write sections, such as the data section and stack,
1767 are still copied to RAM. The XIP kernel is not compressed since
1768 it has to run directly from flash, so it will take more space to
1769 store it. The flash address used to link the kernel object files,
1770 and for storing it, is configuration dependent. Therefore, if you
1771 say Y here, you must know the proper physical address where to
1772 store the kernel image depending on your own flash memory usage.
1774 Also note that the make target becomes "make xipImage" rather than
1775 "make zImage" or "make Image". The final kernel binary to put in
1776 ROM memory will be arch/arm/boot/xipImage.
1780 config XIP_PHYS_ADDR
1781 hex "XIP Kernel Physical Location"
1782 depends on XIP_KERNEL
1783 default "0x00080000"
1785 This is the physical address in your flash memory the kernel will
1786 be linked for and stored to. This address is dependent on your
1790 bool "Kexec system call (EXPERIMENTAL)"
1791 depends on EXPERIMENTAL
1793 kexec is a system call that implements the ability to shutdown your
1794 current kernel, and to start another kernel. It is like a reboot
1795 but it is independent of the system firmware. And like a reboot
1796 you can start any kernel with it, not just Linux.
1798 It is an ongoing process to be certain the hardware in a machine
1799 is properly shutdown, so do not be surprised if this code does not
1800 initially work for you. It may help to enable device hotplugging
1804 bool "Export atags in procfs"
1808 Should the atags used to boot the kernel be exported in an "atags"
1809 file in procfs. Useful with kexec.
1812 bool "Build kdump crash kernel (EXPERIMENTAL)"
1813 depends on EXPERIMENTAL
1815 Generate crash dump after being started by kexec. This should
1816 be normally only set in special crash dump kernels which are
1817 loaded in the main kernel with kexec-tools into a specially
1818 reserved region and then later executed after a crash by
1819 kdump/kexec. The crash dump kernel must be compiled to a
1820 memory address not used by the main kernel
1822 For more details see Documentation/kdump/kdump.txt
1824 config AUTO_ZRELADDR
1825 bool "Auto calculation of the decompressed kernel image address"
1826 depends on !ZBOOT_ROM && !ARCH_U300
1828 ZRELADDR is the physical address where the decompressed kernel
1829 image will be placed. If AUTO_ZRELADDR is selected, the address
1830 will be determined at run-time by masking the current IP with
1831 0xf8000000. This assumes the zImage being placed in the first 128MB
1832 from start of memory.
1836 menu "CPU Power Management"
1840 source "drivers/cpufreq/Kconfig"
1843 tristate "CPUfreq driver for i.MX CPUs"
1844 depends on ARCH_MXC && CPU_FREQ
1846 This enables the CPUfreq driver for i.MX CPUs.
1848 config CPU_FREQ_SA1100
1851 config CPU_FREQ_SA1110
1854 config CPU_FREQ_INTEGRATOR
1855 tristate "CPUfreq driver for ARM Integrator CPUs"
1856 depends on ARCH_INTEGRATOR && CPU_FREQ
1859 This enables the CPUfreq driver for ARM Integrator CPUs.
1861 For details, take a look at <file:Documentation/cpu-freq>.
1867 depends on CPU_FREQ && ARCH_PXA && PXA25x
1869 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1871 config CPU_FREQ_S3C64XX
1872 bool "CPUfreq support for Samsung S3C64XX CPUs"
1873 depends on CPU_FREQ && CPU_S3C6410
1878 Internal configuration node for common cpufreq on Samsung SoC
1880 config CPU_FREQ_S3C24XX
1881 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1882 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1885 This enables the CPUfreq driver for the Samsung S3C24XX family
1888 For details, take a look at <file:Documentation/cpu-freq>.
1892 config CPU_FREQ_S3C24XX_PLL
1893 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1894 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1896 Compile in support for changing the PLL frequency from the
1897 S3C24XX series CPUfreq driver. The PLL takes time to settle
1898 after a frequency change, so by default it is not enabled.
1900 This also means that the PLL tables for the selected CPU(s) will
1901 be built which may increase the size of the kernel image.
1903 config CPU_FREQ_S3C24XX_DEBUG
1904 bool "Debug CPUfreq Samsung driver core"
1905 depends on CPU_FREQ_S3C24XX
1907 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1909 config CPU_FREQ_S3C24XX_IODEBUG
1910 bool "Debug CPUfreq Samsung driver IO timing"
1911 depends on CPU_FREQ_S3C24XX
1913 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1915 config CPU_FREQ_S3C24XX_DEBUGFS
1916 bool "Export debugfs for CPUFreq"
1917 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1919 Export status information via debugfs.
1923 source "drivers/cpuidle/Kconfig"
1927 menu "Floating point emulation"
1929 comment "At least one emulation must be selected"
1932 bool "NWFPE math emulation"
1933 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1935 Say Y to include the NWFPE floating point emulator in the kernel.
1936 This is necessary to run most binaries. Linux does not currently
1937 support floating point hardware so you need to say Y here even if
1938 your machine has an FPA or floating point co-processor podule.
1940 You may say N here if you are going to load the Acorn FPEmulator
1941 early in the bootup.
1944 bool "Support extended precision"
1945 depends on FPE_NWFPE
1947 Say Y to include 80-bit support in the kernel floating-point
1948 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1949 Note that gcc does not generate 80-bit operations by default,
1950 so in most cases this option only enlarges the size of the
1951 floating point emulator without any good reason.
1953 You almost surely want to say N here.
1956 bool "FastFPE math emulation (EXPERIMENTAL)"
1957 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1959 Say Y here to include the FAST floating point emulator in the kernel.
1960 This is an experimental much faster emulator which now also has full
1961 precision for the mantissa. It does not support any exceptions.
1962 It is very simple, and approximately 3-6 times faster than NWFPE.
1964 It should be sufficient for most programs. It may be not suitable
1965 for scientific calculations, but you have to check this for yourself.
1966 If you do not feel you need a faster FP emulation you should better
1970 bool "VFP-format floating point maths"
1971 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1973 Say Y to include VFP support code in the kernel. This is needed
1974 if your hardware includes a VFP unit.
1976 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1977 release notes and additional status information.
1979 Say N if your target does not have VFP hardware.
1987 bool "Advanced SIMD (NEON) Extension support"
1988 depends on VFPv3 && CPU_V7
1990 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1995 menu "Userspace binary formats"
1997 source "fs/Kconfig.binfmt"
2000 tristate "RISC OS personality"
2003 Say Y here to include the kernel code necessary if you want to run
2004 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2005 experimental; if this sounds frightening, say N and sleep in peace.
2006 You can also say M here to compile this support as a module (which
2007 will be called arthur).
2011 menu "Power management options"
2013 source "kernel/power/Kconfig"
2015 config ARCH_SUSPEND_POSSIBLE
2016 depends on !ARCH_S5P64X0 && !ARCH_S5P6442
2017 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2018 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2023 source "net/Kconfig"
2025 source "drivers/Kconfig"
2029 source "arch/arm/Kconfig.debug"
2031 source "security/Kconfig"
2033 source "crypto/Kconfig"
2035 source "lib/Kconfig"